IBM Personal Computer 6268 User Manual

Technical Information Manual

PC 300GL Types 6268, 6278, and 6288

Contents

Preface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Related publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Terminology usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Chapter 1. System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Major features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Network support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Wake on LAN

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Wake on Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2. System board features

Celeron microprocessor with MMX technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Features

L2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chip set control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IDE bus master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USB interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Low pin count (LPC) bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Video subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Graphics memory controller hub (Super Video Graphics Array)

. . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Video memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Monitor support

Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Super input/output controller

Diskette drive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Parallel port

Keyboard and mouse ports

Network connection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Real-time clock and CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Expansion adapters

Physical layout

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

System board, types 6268, 6278, and 6288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Cable connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Connector panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 3. Physical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PC 300GL — desktop

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PC 300GL — tower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Cabling requirements for Wake on LAN adapters

Chapter 4. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power output

Component outputs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

 Copyright IBM Corp. September 1999

iii

Output protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Connector description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 5. System software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Plug and Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

POST

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Advanced Power Management (APM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Configuration/Setup Utility program

Advanced Configuration and Power Interface

Flash update utility program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Diagnostic program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 6. System compatibility

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Hardware compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Diskette drives and controller

Hard disk drives and controller

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Software compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Software interrupts

Machine-sensitive programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Appendix A. Connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Monitor connector

Memory connectors

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PCI connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

IDE connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Diskette drive connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Power supply connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Modem/Ring Wakeup and Wake on LAN connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

USB port connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mouse and keyboard port connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Serial port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Parallel port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Appendix B. System address maps

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

System memory map

Input/output address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DMA I/O address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PCI configuration space map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Appendix C. IRQ and DMA channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Appendix D. Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

POST error codes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

POST beep codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Appendix E. Notices and trademarks

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

iv Technical Information Manual

Figures

1. Memory configurations

2. Video subsystem resources

3. Supported VGA video modes

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4. Supported Enhanced VGA video modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5. Serial port assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6. Parallel port assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7. BIOS configuration jumper (J7A1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8. Power Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9. Power Output (145 Watt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10. System board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

11. Keyboard port

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

12. Auxiliary device port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

13. PCI-bus adapters (Per Slot) either/or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

14. USB port

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15. Internal DASD

16. Video port pin 9

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

17. 3.5-inch diskette drive reading, writing, and formatting capabilities . . . . . . . . . . . . . . . . . . 23

18. Monitor port connector pin assignments

19. System Memory Connector Pin Assignments

20. System memory connector pin input/output

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

21. PCI bus connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

22. PCI connector pin assignments

23. IDE connector pin assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

24. Diskette Drive Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

25. Power Supply Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

26. J13 Modem/Ring Wakeup Connector Pin Assignments

27. J22 Wake on LAN Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

28. USB Port Connector Pin Assignments

. . . . . . . . . . . . . . . . . . . . . . . . 33

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

29. Mouse port connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

30. Keyboard port connector pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

31. Serial Port Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

32. Parallel port connector pin assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

33. System memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

34. I/O address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

35. DMA I/O address map

36. IRQ channel assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

37. DMA channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

 Copyright IBM Corp. September 1999

Preface

This Technical Information Manual provides information for the IBM PC 300GL Types 6268, 6278, and

6288. It is intended for developers who want to provide hardware and software products to operate with

these IBM computers and provides an in-depth view of how these IBM computers work. Users of this

publication should have an understanding of computer architecture and programming concepts.

Related publications

In addition to this manual, the following IBM publications provide information related to the operation of the

IBM PC 300GL.

Ÿ PC 300GL User Guide

This publication contains information about configuring, operating, and maintaining the PC 300GL, as

well as installing new options in the PC 300GL. Also included are warranty information, instructions

for diagnosing and solving problems, and information on how to obtain help and service.

Ÿ Understanding Your Personal Computer

This online document includes general information about using computers and detailed information

about the features of the PC 300GL.

Ÿ About Your Software

This publication (provided only with computers that have IBM-preinstalled software) contains

information about the preinstalled software package.

Ÿ Hardware Maintenance Manual

This publication contains information for trained service technicians. It is available at

http://www.ibm.com/pc/us/cdt/hmm.html on the World Wide Web, and it can also be ordered from IBM.

To purchase a copy, refer to the "Getting Help, Service, and Information" section in PC 300GL User

Guide.

Ÿ Compatibility Report

This publication contains information about compatible hardware and software for the PC 300GL. It is

available at http://www.ibm.com/pc/us/cdt on the World Wide Web.

Ÿ Network Administrator's Guide

This publication contains information for network administrators who configure and service local area

networks (LANs). Look for this publication at http://www.ibm.com/pc/us/cdt on the World Wide Web.

Terminology usage

Attention: The term reserved describes certain signals, bits, and registers that should not be changed.

Use of reserved areas can cause compatibility problems, loss of data, or permanent damage to the

hardware. When the contents of a register are changed, the state of the reserved bits must be preserved.

When possible, read the register first and change only the bits that must be changed.

In this manual, some signals are represented in a small, all-capital-letter format (-ACK). A minus sign in

front of the signal indicates that the signal is active low. No sign in front of the signal indicates that the

signal is active high.

The use of the term hex indicates a hexadecimal number. Also, when numerical modifiers such as “K”,

“M” and “G“ are used, they typically indicate powers of 2, not powers of 10. For example, 1 KB equals

1024 bytes (2 ¹⁰), 1 MB equals 1048576 bytes (2 ²⁰), and 1 GB equals 1073741824 bytes (2 ³⁰).

 Copyright IBM Corp. September 1999

When expressing storage capacity, MB equals 1000 KB (1024000). The value is determined by counting

the number of sectors and assuming that every two sectors equals 1 KB.

Note: Depending on the operating system and other system requirements, the storage capacity available

to the user might vary.

Preface vii

viii Technical Information Manual

Chapter 1. System overview

PC 300GL Types 6268, 6278, and 6288 are computer systems designed to provide state-of-the-art

computing power with room for future growth.

Major features

The major features are:

Ÿ An Intel^Celeron^microprocessor with MMX technology, with 128 KB L2 cache

Ÿ Up to 512 MB of system memory

Ÿ Integrated IDE bus master controller, ATA 66 capable

Ÿ EIDE hard disk drive

Ÿ System management

– Wake on LAN support

– DMI (Desktop Management Interface) BIOS and DMI software

– Integrated network protocols

– Enablement for remote administration

– Universal Management Agent (UMA) and UMA Plus

– Wake on Ring support

Ÿ IDE CD-ROM¹drive, standard on some models

Ÿ Asset security

– Security settings provided by the Configuration/Setup Utility program

- Power-on and administrator password protection

- Startup sequence control

- Hard disk drive and diskette drive access control

- I/O port control

– Cover lock loop

– U-bolt and security cabling (optional)

– Operating system security

– Diskette write-protection

– Alert on LAN support

Ÿ Integrated video controller with 4 MB of video display cache memory

Ÿ Integrated 16-bit, stereo Analog Devices, Inc. audio controller and built-in high quality speaker in all

models (supports SoundBlaster, DirectX, and Microsoft Windows Sound System applications)

Ÿ Networking

– IBM 10/100 Mbits per second (Mbps), PCI Ethernet adapter with Wake on LAN in some models.

– IBM PCI token ring adapter with Wake on LAN is optional.

Ÿ Expansion: Four drive bays, four PCI expansion slots

Ÿ PCI I/O bus compatibility

Ÿ EnergyStar compliance

Variable read rate. Actual playback speed will vary and is often less than the maximum possible.

 Copyright IBM Corp. September 1999

Chapter 1. System overview

Ÿ 3.5-inch, 1.44 MB diskette drive

Ÿ Input/output features

– One 25-pin, parallel port with Extended Capabilities Port (EPP)/Extended Parallel Port (EPP)

support

– Two 9-pin, Universal asynchronous receiver/transmitter (UART) serial ports

– Two 4-pin, Universal Serial Bus (USB) ports

– One 6-pin, keyboard port (PS/2 compatible)

– One 6-pin, mouse port

– One 15-pin, DDC2B-compliant monitor port

– Three 3.5 mm audio jacks (line/headphone out, line in, microphone)

Other features

The following features might be supported by the PC 300GL.

Network support

PC 300GL computers are enabled to support management over a network. The following is a list of

supported functions:

Ÿ Selectable startup sequence

Ÿ Selectable Automatic Power On Startup Sequence

Ÿ Update POST/BIOS from network

Ÿ Wake on LAN

Ÿ CMOS Save/Restore utility program

Ÿ CMOS setup over LAN

Ÿ Wake on Ring

Wake on LAN

The power supply of the computer supports the Wake on LAN feature. With the Wake on LAN feature,

the computer can be turned on when a specific LAN frame is passed to the PC over the LAN.

To use the Wake on LAN feature, the computer must be equipped with a network adapter that supports

Wake on LAN. Some models come with a network adapter that supports Wake on LAN.

You can find the menu used for setting the Wake on LAN feature in the Configuration/Setup Utility

program.

Wake on Ring

All models are configurable to turn on the computer after a ring is detected from an external or internal

modem. The menu used for setting the Wake Up on Ring feature is found in the Configuration/Setup

Utility program. Two options control this feature:

Ÿ Serial Ring Detect: Use this option if the computer has an external modem connected to serial port

Ÿ Modem Ring Detect: Use this option if the computer has an internal modem that supports the Wake

on Ring feature.

Technical Information Manual

Chapter 2. System board features

This section includes information about system board features. For an illustration of the system board,

see “System board, types 6268, 6278, and 6288” on page 13.

Celeron microprocessor with MMX technology

PC 300GL Types 6268, 6278, and 6288 comes with an Intel Celeron microprocessor. The

microprocessor, which has a heat sink attached, plugs directly into a connector on the system board.

More information about this microprocessor is available at http://www.intel.com on the World Wide Web.

Features

The features of this microprocessor are as follows:

Ÿ Optimization for 32-bit software

Ÿ Operation at a lower voltage level than previous microprocessors

Ÿ 64-bit microprocessor data bus

Ÿ 66 MHz FSB

Ÿ 128 KB L2 cache integrated into the microprocessor

Ÿ Cache operates at processor core speed

– 4-way set associative

– Nonblocking

Ÿ 32-bit microprocessor address bus

Ÿ Math coprocessor

Ÿ MMX technology, which boosts the processing of graphic, video, and audio data

L2 cache

The Celeron microprocessor provides 128 KB L2 cache. (For information on overriding settings, see

Configuration/Setup Utility program, in PC 300GL User Guide.)

Chip set control

The Intel 810 chip set is the interface between the microprocessor and the following:

Ÿ Memory subsystem

Ÿ PCI bus

Ÿ IDE Bus Master connection

Ÿ Low Pin Count (LPC) bus

Ÿ USB ports

Ÿ SMBus

Ÿ Enhanced DMA controller

Ÿ Real-time clock (RTC)

Ÿ Audio coder/decoder (codec)

 Copyright IBM Corp. September 1999

Chapter 2. System board features

System memory

The system memory interface is controlled by the Intel 82810 chip set. PCI 100 synchronous dynamic

random access memory (SDRAM) is standard.

The maximum amount of system memory is 512 MB. For memory expansion, the system board provides

two dual inline memory module (DIMM) connectors. 100 MHz DIMMs in sizes of 32 MB, 64 MB, 128 MB,

and 256 MB are supported. The amount of memory preinstalled varies by model.

The following information applies to system memory:

Ÿ SDRAM, nonparity, unbuffered, 3.3V memory is standard.

Ÿ The maximum height of memory modules is 6.35 cm (2.5 in.).

Ÿ Only PC 100 industry-standard, gold-contact DIMMs are supported.

Ÿ The PC 300GL does not support error correcting code (ECC).

Ÿ Auto-configure, auto-detect maximum system memory, using serial presence detect and configuration

interface (BIOS specific).

For information on the pin assignments for the memory module connectors, see “Memory connectors” on

page 25.

The following figure shows some possible configurations for the supported DIMMs.

Note: Values in the following table are represented in megabytes (MB).

Figure 1. Memory configurations

Total memory (MB)

DIMM 0

DIMM 1

128

160

192

256

384

512

128

256

128

256

PCI bus

The fully synchronous 33 MHz PCI bus originates in the Intel 82801 chip. Features of the PCI bus are:

Ÿ Integrated arbiter with multitransaction PCI arbitration acceleration hooks

Ÿ Zero-wait-state, microprocessor-to-PCI write interface for high performance graphics

Ÿ Built-in PCI bus arbiter with support for up to five masters

Ÿ Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers

Ÿ Converts back-to-back sequential microprocessor-to-PCI memory write to PCI burst write

Ÿ PCI-to-DRAM posting 18 Dwords

Ÿ PCI-to-DRAM up to 100+ MB/sec bandwidth

Ÿ Multitransaction timer to support multiple short PCI transactions within one PCI ARB cycle

Ÿ PCI 2.2/2.3 compliant

Technical Information Manual

Chapter 2. System board features

Ÿ Delayed transaction

Ÿ PCI parity checking and generation support

IDE bus master interface

The system board incorporates a PCI-to-IDE interface that complies with the AT Attachment Interface with

Extensions.

The bus master for the IDE interface is integrated into the I/O hub of the Intel 810 chipset. The chip set is

PCI 2.1 compliant. It connects directly to the PCI bus and is designed to allow concurrent operations on

the PCI bus and IDE bus. The chip set is capable of supporting PIO mode 0–4 devices and IDE DMA

mode 0–3 devices, ATA 66 transfers up to 66 Mbytes/sec.

The IDE devices receive their power through a four-position power cable containing +5, +12, and ground

voltage. When adding devices to the IDE interface, one device is designated as the master device and

another is designated as the slave or subordinate device. These designations are determined by switches

or jumpers on each device. There are two IDE ports, one designated 'Primary' and the other 'Secondary,'

allowing for up to four devices to be attached. The total number of physical IDE devices is dependent on

the mechanical package to a maximum of four.

For the IDE interface, no resource assignments are given in the system memory or the direct memory

access (DMA) channels. For information on the resource assignments, see “Input/output address map” on

page 36 and Figure 36 on page 40 (for IRQ assignments).

USB interface

Universal serial bus (USB) technology is a standard feature of the computer. The system board provides

the USB interface with two connectors integrated into the ICH (I/O controller hub) in the chip set. A

USB-enabled device can attach to each connector, and if that device is a hub, multiple peripherals can

attach to the hub and be used by the system. The USB connectors use Plug and Play technology for

installed devices. The speed of the USB is up to 12 Mbps with a maximum of 127 peripherals. The USB

is compliant with Universal Host Controller Interface Guide 1.0.

Features provided by USB technology include:

Ÿ Support for hot-pluggable devices

Ÿ Support for concurrent operation of multiple devices

Ÿ Suitable for different device bandwidths

Ÿ Support for up to five meters length from host to hub or from hub to hub

Ÿ Guaranteed bandwidth and low latencies appropriate for specific devices

Ÿ Wide range of packet sizes

Ÿ Limited power to hubs

For information on the connector pin assignments for the USB interface, see “USB port connectors” on

page 33.

Low pin count (LPC) bus

On the system board, the Intel ICH1 bridge provides the interface between the peripheral component

interface (PCI) and LPC buses. The chip set is used to convert PCI bus cycles to ISA bus cycles; the

chip set also includes all the subsystems of the ISA bus, including two cascaded interrupt controllers, two

DMA controllers with four 8-bit and three 16-bit channels, three counters equivalent to a programmable

interval timer, and power management. The PCI bus operates at 33 MHz.

Chapter 2. System board features

Video subsystem

The video subsystem includes the Intel 810 graphics controller integrated in the Graphics Memory

Controller Hub (GMCH) and 4MB of 100MHz local graphics display cache SDRAM.

Graphics memory controller hub (Super Video Graphics Array)

The video subsystem uses system memory for display buffer, commands, and 3D textures on

AGP-enabled operating systems via Dynamic Video Memory Technology (DVMT). The Intel 810 graphics

controller drivers will adjust the memory footprint depending on available system memory, current desktop

resolution, and presence of the display cache local memory. DVMT employs direct AGP and intelligent

arbitration to dynamically allocate and deallocate memory for textures for applications requiring additional

texture memory.

The operating system requires allocation of up to 1MB of system memory to support legacy VGA. System

properties will display up to 1MB less than physical system memory available to the operating system.

The integrated graphics memory controller hub supports all video graphics array (VGA) modes and is

compliant with super video graphics array (SVGA) modes and Video Electronics Standards Association

(VESA) 1.2. Some of the features are:

Ÿ 2D and 3D hardware acceleration with hardware cursor

Ÿ Integrated 230 MHz RAMDAC for up to 1600x1200 at 85Hz resolution

Ÿ Hardware Motion Compensation via Intel HWMC Software Development Kit

Ÿ Advanced Power Management (APM)

Ÿ Advanced Configuration and Power Interface (ACPI)

Ÿ On Now (Suspend to RAM)

Ÿ Plug and Play

Ÿ VESA Display Data Channel version DDC2B

Ÿ GDI, Direct X, and OpenGL v1.1 Application Programming Interfaces

The integrated graphics memory controller subsystem supports the VESA Display Data Channel (DDC)

standard 1.1 and uses DDC1 and DDC2B to determine optimal values during automatic monitor detection.

The video subsystem has the following resource assignments:

Figure 2. Video subsystem resources

Resource

Assignment

ROM (hex)

RAM (hex)

I/O (hex)

IRQ

C0000–C7FFF (32KB)

A0000–BFFFF

3B0–3BB, 3C0–3DF

PCI interrupt #A (default assigned to ISA IRQ #1)

None

DMA

For further information on resource assignments, see Appendix B, “System address maps” on page 36

and Appendix C, “IRQ and DMA channel assignments” on page 40.

Technical Information Manual

Chapter 2. System board features

The PC 300GL supports the following video subsystem modes:

Figure 3. Supported VGA video modes

Mode (hex)

Display Mode

Screen Resolution

Colors

Refresh Rate

(Hz)

Text

40 x 25 characters

80 x 25 characters

320 x 200 pixels

640 x 200 pixels

80 x 25 characters

320 x 200 pixels

640 x 200 pixels

640 x 350 pixels

640 x 480 pixels

320 x 200 pixels

B/W

Text

B/W

Text

Graphics

Text

Mono

Graphics

Mono

256

Figure 4 (Page 1 of 3). Supported Enhanced VGA video modes

Mode (hex)

Display Mode

Screen Resolution

Colors

Refresh Rate

(Hz)

100

101

102

103

105

107

Graphics

640x400

640x480

800x600

1024x768

1280x1024

Chapter 2. System board features

Figure 4 (Page 2 of 3). Supported Enhanced VGA video modes

Mode (hex)

Display Mode

Screen Resolution

Colors

Refresh Rate

(Hz)

107

108

109

10A

10B

10C

110

111

112

113

114

115

116

Graphics

Text

1280x1024

132x25 chars

132x43 chars

132x50 chars

132x60 chars

640x480

Text

Graphics

640x480

800x600

1024x768

Technical Information Manual

Chapter 2. System board features

Figure 4 (Page 3 of 3). Supported Enhanced VGA video modes

Mode (hex)

Display Mode

Screen Resolution

Colors

Refresh Rate

(Hz)

117

118

119

11A

11B

Graphics

1024x768

1280x1024

600X1200

1600X1200

Monitor support

The video subsystem provides a 15-pin monitor connector on the system board. For information on

connector pin assignments, see Appendix A, “Connector pin assignments” on page 25.

Video memory

The video subsystem has 4MB of 100MHz SDRAM on the system board for 2D and 3D graphics display

cache.

Chapter 2. System board features

Audio subsystem

Some PC 300GL models come with an Analog Devices, Inc. integrated audio controller. These models,

which are capable of playing and recording sounds, support DirectX and Microsoft Windows Sound

System applications. SoundBlaster applications are supported in a DOS window only.

The device drivers for the audio controller are on the hard disk drive. The device drivers are also

available on the Software Selections CD provided with all models.

The following connectors are available on the audio adapter or integrated audio controller:

Ÿ Line/Headphone out port for connecting powered speakers. Your audio system requires a set of

speakers or headphones connected to the Line/Headphone out port in order to hear audio from the

system. These speakers must be powered with a built-in amplifier. In general, any powered speakers

designed for use with personal computers can be used with your audio system. These speakers are

available with a wide range of features and power outputs.

Ÿ Line in port for connecting musical devices, such as a portable CD-ROM or stereo system.

Ÿ Microphone for connecting a microphone.

Super input/output controller

Control of the integrated input/output (I/O) and diskette drive controllers is provided by a single module,

the Super Input/Output Controller. This module supports Plug and Play and controls the following

features:

Ÿ Diskette drive interface

Ÿ Serial port

Ÿ Parallel port

Ÿ Keyboard and mouse ports

Ÿ General purpose I/O ports

Diskette drive interface

The following is a list of devices that the diskette drive subsystem supports:

Ÿ 1.44 MB, 3.5 inch diskette drive

Ÿ 1.44 MB, 3.5 inch, 3-mode drive for Japan (no BIOS support for 3-mode drive)

Ÿ 1 Mbps, 500 Kbps, or 250 Kbps internal tape drive

One connector is provided on the system board for diskette drive support. For information on the

connector pin assignments, see “Diskette drive connector” on page 32.

Serial ports

Two universal asynchronous receiver/transmitter (UART) serial port are integrated into the system board.

The serial ports include 16-byte data, first-in first-out (FIFO) buffers and have programmable baud rate

generators. The serial ports are NS16450 and PC16550A compatible.

For information on the connector pin assignments, see “Serial port connector” on page 34.

Note: Current loop interface is not supported.

The following figure shows the serial port assignments in the configuration.

10 Technical Information Manual

Chapter 2. System board features

Figure 5. Serial port assignments

Port assignment

Serial 1

Address range (hex)

03F8–03FF

IRQ level

IRQ4

Serial 2

02F8–02FF

IRQ3

Serial 3

03E8–03FF

IRQ4

Serial 4

02E8–02FF

IRQ3

The default setting for the serial port is COM1.

Parallel port

Integrated in the system board is support for extended capabilities port (ECP), enhanced parallel port

(EPP), and standard parallel port (SPP) modes. The modes of operation are selected through the

Configuration/Setup Utility program with the default mode set to ECP. The ECP and EPP modes are

compliant with IEEE 1284.

The following figure shows the parallel port assignments used in the configuration.

Figure 6. Parallel port assignments

Port assignment

Parallel 1

Address range (hex)

03BC–03BE

IRQ level

IRQ7

Parallel 2

0378–037F

IRQ5

Parallel 3

0278–027F

IRQ5

The default setting for the parallel port is Parallel 1.

The system board has one connector for the parallel port. For information on the connector pin

assignments, see “Parallel port connector” on page 34.

Keyboard and mouse ports

The keyboard and mouse subsystem is controlled by a general purpose 8-bit microcontroller; it is

compatible with 8042AH. The controller consists of 256 bytes of data memory and 2 KB of read-only

memory (ROM).

The controller has two logical devices: one controls the keyboard and the other controls the mouse. The

keyboard has two fixed I/O addresses and a fixed IRQ line and can operate without the mouse. The

mouse cannot operate without the keyboard because, although it has a fixed IRQ line, the mouse relies on

the addresses of the keyboard for operation. For the keyboard and mouse interfaces, no resource

assignments are given in the system memory addresses or DMA channels. For information on the

resource assignments, see “Input/output address map” on page 36 and Figure 36 on page 40 (for IRQ

assignments).

The system board has one connector for the keyboard port and one connector for the mouse port. For

information on the connector pin assignments, see “Mouse and keyboard port connectors” on page 33.

Chapter 2. System board features 11

Chapter 2. System board features

Network connection

Some PC 300GL models are equipped with an Ethernet adapter that supports the Wake on LAN feature.

Features of the optional Ethernet adapter are:

Ÿ Operates in shared 10BASE-T or 100BASE-TX environment

Ÿ Transmits and receives data at 10 Mbps or 100 Mbps

Ÿ RJ-45 connector for LAN attachment

Ÿ Operates in symmetrical multiprocessing (SMP) environments

Ÿ Wake on LAN support

Ÿ Remote Program Load (RPL) and Dynamic Host Configuration Protocol (DHCP) support

Features of the optional token ring adapter are:

Ÿ Transmits and receives data at 4 Mbps or 16 Mbps

Ÿ RJ-45 and D-shell connectors for LAN attachment

Ÿ Wake on LAN support

Ÿ Remote Program Load (RPL) and Dynamic Host Configuration Protocol (DHCP) support

Real-time clock and CMOS

The real-time clock is a low-power clock that provides a time-of-day clock and a calendar. The clock

settings are maintained by an external battery source of 3 V DC.

The system uses 242 bytes of memory to store complementary metal-oxide semiconductor (CMOS)

memory. Moving a jumper on the system board erases CMOS memory.

To locate the battery, see “System board, types 6268, 6278, and 6288” on page 13.

Flash EEPROM

The system board uses a 2 MB flash electrically erasable, programmable, read-only memory (EEPROM)

to store the basic input/output system (BIOS), video BIOS, IBM logo, Configuration/Setup Utility, and Plug

and Play data.

If necessary, the EEPROM can be easily updated using a stand-alone utility program that is available on a

3.5-inch diskette.

Expansion adapters

Each PCI-expansion connector is a 32–bit slot. PCI-expansion connectors support the 32–bit 5 V DC,

local-bus signalling environment that is defined in PCI Local Bus Specification 2.2.

The PC 300GL has four PCI slots to support the addition of adapters. For information on installing

adapters, see PC 300GL User Guide. For information on the connector pin assignments, see “PCI

connectors” on page 29.

12 Technical Information Manual

Chapter 2. System board features

Physical layout

The system board might look slightly different from the one shown.

Note: A diagram of the system board, including switch and jumper settings, is attached to the underside

of the computer cover.

System board, types 6268, 6278, and 6288

.1/Microprocessor

.2/DIMM 0

.3/DIMM 1

.4/Alert on LAN connector

.5/Secondary EIDE connector

.6/Diskette connector

.7/Primary EIDE connector

.8/Power connector

.9/Fan connector

.1ð/Battery

.11/Wake on LAN connector

.12/PC/PCI legacy audio adapter

.13/Clear CMOS/recovery jumper

.14/PCI adapter slot 4

.15/PCI adapter slot 3

.16/PCI adapter slot 2

.17/Chassis speaker connector

.18/PCI adapter slot 1

.19/CD-ROM connector

Jumper

Jumpers on the system board are used for custom configurations. For the location of the CMOS recovery

jumper, refer to the “System board, types 6268, 6278, and 6288,” above.

Figure 7. BIOS configuration jumper (J7A1)

Pins

Description

1 and 2

2 and 3

Normal (Factory default)

Clear CMOS/Password

Cable connectors

Connections for attaching devices are provided on the back of the computer. The connectors are:

Ÿ USB (2)

Ÿ Mouse

Ÿ Keyboard

Ÿ Serial

Ÿ Parallel

Ÿ Monitor

Ÿ Some models only: Ethernet adapter with an RJ-45 connector

Ÿ Integrated Analog Devices, Inc. audio controller with line in, line out, and microphone connectors

Chapter 2. System board features 13

Chapter 2. System board features

Connector panel

Connectors for features that are integrated into the system board can be identified by a symbol directly

below the connector. Connectors provided by an adapter might not have an identifying symbol. For

pinout details on connectors, see Appendix A, “Connector pin assignments” on page 25.

The connector panel for the tower model:

Keyboard

Mouse

USB

Monitor

Printer

Serial 1

Headphone/

Line Out

Line In

Microphone

Serial 2

The connector panel for the desktop model:

Mouse

Serial 2

USB 2

Parallel

Headphone/

Line Out

Keyboard

Monitor

Microphone

Line In

USB 1

Serial 1

14 Technical Information Manual

Chapter 3. Physical specifications

This section lists the physical specifications for the PC 300GL Types 6268, 6278, and 6288. The PC

300GL has four expansion slots and four drive bays.

Notes:

Ÿ The maximum altitude, 2133.6 m (7000 ft.), is the maximum altitude at which the specified air

temperatures apply. At higher altitudes, the maximum air temperatures are lower than those

specified.

Ÿ The PC 300GL computers comply with FCC Class B.

PC 300GL — desktop

Dimensions

Heat output

Ÿ Height: 138 mm (5.43 in.)

Ÿ Width: 400 mm (15.75 in.)

Ÿ Depth: 429 mm (16.9 in.)

Ÿ Approximate heat output in British thermal units (Btu) per

hour:

– Minimum configuration: 256 Btu/hr (75 watts)

– Maximum configuration: 706 Btu/hr (207 watts)

Weight

Airflow

Ÿ Minimum configuration as shipped: 9.53 kg (21 lb)

Ÿ Maximum configuration: 10.4 kg (23 lb)

Ÿ Approximately 0.5 cubic meters per minute (18 cubic feet

per minute)

Environment

Acoustical noise-emission values

Ÿ Air temperature:

– System on: 10° to 35°C (50° to 95°F)

– System off: 10° to 43°C (50° to 110°F)

Ÿ Humidity:

Ÿ Average sound-pressure levels:

– At operator position:

- Idle: 38 dBA

– System on: 8% to 80%

- Operating: 43 dBA

– System off: 8% to 80%

Ÿ Maximum altitude: 2134 m (7000 ft)

– At bystander position–1 meter (3.3 ft):

- Idle: 33 dBA

- Operating: 37 dBA

Ÿ Declared (upper limit) sound power levels:

– Idle: 4.8 bels

Electrical input

Ÿ Input voltage:

– Low range:

– Operating: 5.1 bels

- Minimum: 90 V ac

- Maximum: 137 V ac

- Input frequency range: 57-63 Hz

- Voltage switch setting: 115 V

– High range:

Note: These levels were measured in controlled acoustical

environments according to procedures specified by the

American National Standards Institute (ANSI) S12.10 and

ISO 7779, and are reported in accordance with ISO 9296.

Actual sound-pressure levels in your location might exceed

the average values stated because of room reflections and

other nearby noise sources. The declared sound power

levels indicate an upper limit, below which a large number

of computers will operate.

- Minimum: 180 V ac

- Maximum: 265 V ac

- Input frequency range: 47-53 Hz

- Voltage switch setting: 230 V

– Input kilovolt-amperes (kVA) (approximately):

- Minimum configuration as shipped: 0.08 kVA

- Maximum configuration: 0.51 kVA

Note: Power consumption and heat output vary depending

on the number and type of optional features installed

and the power-management optional features in use.

Note: PC 300GL computers do not support IDE expansion adapters or the IBM PCMCIA adapter for PCI.

 Copyright IBM Corp. September 1999

Chapter 3. Physical specifications

PC 300GL — tower

Dimensions

Heat output

Ÿ Height: 383 mm (15.1 in.)

Ÿ Width: 192 mm (7.6 in.)

Ÿ Depth: 378 mm (14.9 in.)

Ÿ Approximate heat output in British thermal units (Btu) per

hour:

– Minimum configuration: 256 Btu/hr (75 watts)

– Maximum configuration: 706 Btu/hr (207 watts)

Weight

Airflow

Ÿ Minimum configuration as shipped: 8.30 kg (18.3 lb)

Ÿ Maximum configuration: 10.2 kg (22.5 lb)

Ÿ Approximately 0.5 cubic meters per minute (18 cubic feet

per minute)

Environment

Acoustical noise-emission values

Ÿ Air temperature:

– System on: 10° to 35°C (50° to 95°F)

– System off: 10° to 43°C (50° to 110°F)

Ÿ Humidity:

Ÿ Average sound-pressure levels:

– At operator position:

- Idle: 38 dBA

– System on: 8% to 80%

- Operating: 43 dBA

– System off: 8% to 80%

Ÿ Maximum altitude: 2134 m (7000 ft)

– At bystander position–1 meter (3.3 ft):

- Idle: 33 dBA

- Operating: 37 dBA

– Declared (upper limit) sound power levels:

- Idle: 4.8 bels

Electrical input

Ÿ Input voltage:

– Low range:

- Operating: 5.1 bels

- Minimum: 90 V ac

- Maximum: 137 V ac

- Input frequency range: 57-63 Hz

- Voltage switch setting: 115 V

– High range:

Note: These levels were measured in controlled acoustical

environments according to procedures specified by the

American National Standards Institute (ANSI) S12.10 and

ISO 7779, and are reported in accordance with ISO 9296.

Actual sound-pressure levels in your location might exceed

the average values stated because of room reflections and

other nearby noise sources. The declared sound power

levels indicate an upper limit, below which a large number

of computers will operate.

- Minimum: 180 V ac

- Maximum: 265 V ac

- Input frequency range: 47-53 Hz

- Voltage switch setting: 230 V

– Input kilovolt-amperes (kVA) (approximately):

- Minimum configuration as shipped: 0.08 kVA

- Maximum configuration: 0.51 kVA

Note: Power consumption and heat output vary depending

on the number and type of optional features installed

and the power-management optional features in use.

Note: PC 300GL computers do not support IDE expansion adapters or the IBM PCMCIA adapter for PCI.

Cabling requirements for Wake on LAN adapters

The PC 300GL has a 3-pin header on the system board that provides the Auxiliary 5 volts (AUX5) and

wakeup signal connections. Newer Wake on LAN adapters have a single 3-pin header that connects to a

3-pin header on the system board. Some Wake on LAN adapters have two headers: a 3-pin, right-angle

header for providing AUX5, and a 2-pin straight header for connecting the wakeup signal to the system

board. These Wake on LAN adapter options will provide a Y-cable that has the 3-pin system board

connector on one end and splits into the 3-pin and 2-pin connectors required to interface with the card.

16 Technical Information Manual

Chapter 4. Power supply

The power supply requirements are supplied by a 145-watt power supply. The power supply provides

3.3-volt power for the system memory, Super I/O, and core chip set and 5-volt power for PCI adapters, the

hard disk, and diskette drive. Also included is an auxiliary 5-volt (AUX 5) supply to provide power to

power standby circuitry and a Wake on LAN adapter. The power supply converts the AC input voltage

into four DC output voltages and provides power for the following:

Ÿ System board

Ÿ Adapters

Ÿ Internal drives

Ÿ Keyboard and auxiliary devices

Ÿ USB devices

A logic signal on the power connector controls the power supply; the front panel switch is not directly

connected to the power supply.

The power supply connects to the system board with a 2 x 10 connector.

Power input

The following figure shows the input power specifications. The power supply has a manual switch to

select the correct input voltage.

Figure 8. Power Input Requirements

Specification

Measurements

Input voltage, low range

Input voltage, high range

Input frequency

100 (min) to 127 (max) V AC

200 (min) to 240 (max) V AC

50 Hz 3 Hz or 60 Hz 3 Hz

Power output

The power supply outputs shown in the following figures include the current supply capability of all the

connectors, including system board, DASD, PCI, and auxiliary outputs.

Figure 9. Power Output (145 Watt)

Output voltage

+5 volts

Regulation

+5% to −5%

+10% to −10%

+5% to −5%

Minimum current

1.5 A

Maximum current

18.0 A

+12 volts

0.02 A

4.2 A

−12 volts

0.0 A

0.4 A

+3.3 volts

0.0 A

10.0 A

+5 volt (auxiliary)

0.0 A

0.720 A

The total combined 3.3 V and 5 V power should not exceed 100 watts.

 Copyright IBM Corp. September 1999

Chapter 4. Power supply

Component outputs

The power supply provides separate voltage sources for the system board and internal storage devices.

The following figures show the approximate power that is provided for specific system components. Many

components draw less current than the maximum shown.

Figure 10. System board

Supply voltage

+3.3 V DC

Maximum current

3000 mA

Regulation limits

+5.0% to −5.0%

+5.0% to −4.0%

+5.0% to −5.0%

+10.0% to −9.0%

+5.0 V DC

4000 mA

+12.0 V DC

−12.0 V DC

25.0 mA

Figure 11. Keyboard port

Supply voltage

Maximum current

Regulation limits

+5.0 V DC

275 mA

+5.0% to −4.0%

Figure 12. Auxiliary device port

Supply voltage

Maximum current

Regulation limits

+5.0 V DC

300 mA

+5.0% to −4.0%

Figure 13. PCI-bus adapters (Per Slot) either/or

Supply voltage

+5.0 V dc

Maximum current

Regulation limits

+5.0% to −4.0%

2000 mA

3030 mA

+3.3 V dc

Note: For each PCI connector, the maximum power consumption is rated at 10 watts for +5 V dc and

+3.3 V dc combined. Typical power budget assumptions use 7.5 watts per adapter. If maximum

power is used, then the overall system configuration will be limited in performance.

Figure 14. USB port

Supply voltage

Maximum current

Regulation limits

+5.0 V DC

500 mA

+5.0% to −4.0%

Figure 15. Internal DASD

Supply voltage

+5.0 V DC

Maximum current

Regulation limits

+5.0% to −5.0%

1400 mA

+12.0 V DC

1500 mA at startup, 400 mA when

active

Figure 16. Video port pin 9

Supply voltage

Maximum current

Regulation limits

+5.0 V DC

1100mA

+5.0% to − 5.0%

18 Technical Information Manual

Chapter 4. Power supply

Note: Some adapters and hard disk drives draw more current than the recommended limits. These

adapters and drives can be installed in the system; however, the power supply will shut down if the

total power used exceeds the maximum power that is available.

Output protection

The power supply protects against output overcurrent, overvoltage, and short circuits. See the power

supply specifications on the previous pages for details.

A short circuit that is placed on any dc output (between outputs or between an output and DC return)

latches all dc outputs into a shutdown state, with no damage to the power supply. If this shutdown state

occurs, the power supply returns to normal operation only after the fault has been removed and the power

switch has been turned off for at least one second.

If an overvoltage fault occurs (in the power supply), the power supply latches all DC outputs into a

shutdown state before any output exceeds 130% of the nominal value of the power supply.

Connector description

The power supply for the PC 300GL has four, 4-pin connectors for internal devices. The total power used

by the connectors must not exceed the amount shown in “Component outputs” on page 18. For

connector pin assignments, see Appendix A, “Connector pin assignments” on page 25.

Chapter 4. Power supply 19

Chapter 5. System software

This section briefly describes some of the system software included with the computer.

BIOS

The computer uses the IBM basic input/output system (BIOS), which is stored in flash electrically erasable

programmable read-only memory (EEPROM). Some features of the BIOS are:

Ÿ PCI support according to PCI BIOS Specification 2.2

Ÿ Microsoft's PCI IRQ Routing Table

Ÿ Plug and Play support according to Plug and Play BIOS Specification 1.1a

Ÿ Advanced Power Management (APM) support according to APM BIOS Interface Specification 1.2

Ÿ Wake on LAN support

Ÿ Wake on Ring support

Ÿ Remote Program Load (RPL) and Dynamic Host Configuration Protocol (DHCP)

Ÿ Startable CD-ROM support

Ÿ Flash-over-LAN support

Ÿ Alternate Startup Sequence

Ÿ IBM Look and Feel – Screen arrangements, etc.

Ÿ ACPI (Advanced Configuration and Power Interfaces)

Ÿ IDE Logical Block Addressing (LBA support)

Ÿ LSA 2.0 support

Ÿ Bootable CD ROM support

Ÿ LS120 support

Ÿ DM BIOS 2.1 (DMI 2.0 compliant)

Ÿ PC98 compliant

Plug and Play

Support for Plug and Play conforms to the following:

Ÿ Plug and Play BIOS Specification 1.1a and 1.0

Ÿ Plug and Play BIOS Extension Design Guide 1.0

Ÿ Plug and Play BIOS Specification, Errata, and Clarifications 1.0

Ÿ Guide to Integrating the Plug and Play BIOS Extensions with system BIOS 1.2

Ÿ Plug and Play Kit for DOS and Windows

POST

IBM power-on self-test (POST) code is used. Also, initialization code is included for the on-board system

devices and controllers.

POST error codes include text messages for determining the cause of an error. For more information, see

Appendix D, “Error codes” on page 41.

 Copyright IBM Corp. September 1999

Chapter 5. System software

Configuration/Setup Utility program

The Configuration/Setup Utility program provides menus for selecting options for devices, I/O ports, date

and time, system security, start options, advanced setup, and power management.

More information on using the Configuration/Setup Utility program is provided in PC 300GL User Guide.

Advanced Power Management (APM)

The PC 300GL computers come with built-in energy-saving capabilities. Advanced Power Management

(APM) is a feature that reduces the power consumption of systems when they are not being used. When

enabled, APM initiates reduced-power modes for the monitor, microprocessor, and hard disk drive after a

specified period of inactivity.

The BIOS supports APM 1.2. This enables the system to enter a power-managed state, which reduces

the power drawn from the AC wall outlet. Advanced Power Management is enabled through the

Configuration/Setup Utility program and is controlled by the individual operating system.

For more information on APM, see PC 300GL User Guide and Understanding Your Personal Computer.

Advanced Configuration and Power Interface

Advanced Configuration and Power Interface (ACPI) BIOS mode enables the operating system to control

the power management features of your computer. Not all operating systems support ACPI BIOS mode.

See your operating system documentation to determine if ACPI is supported. ACPI is enabled by default

if your computer comes with Windows 98 preinstalled.

Flash update utility program

The flash update utility program is a stand-alone program to support flash updates. This utility program

updates the BIOS code in flash and the Machine Readable Information (MRI) to different languages.

The flash update utility program is available on a 3.5 inch diskette.

Diagnostic program

The diagnostic program that comes with PC 300PL and PC 300GL computers is provided as a startable

IBM Enhanced Diagnostic diskette image on the IBM Software Selection CD. It runs independently of the

operating system. The user interface for running the diagnostics and utilities is provided by WaterGate

Software's PC-Doctor. It can also be downloaded from

http://www.ibm.com/pc/support/desktop/desktop_support.html on the World Wide Web. For more

information on this diagnostic program, see PC 300GL User Guide.

Chapter 5. System software 21

Chapter 6. System compatibility

This chapter discusses some of the hardware, software, and BIOS compatibility issues for the computer.

Refer to Compatibility Report for a list of compatible hardware and software options.

Hardware compatibility

This section discusses hardware, software, and BIOS compatibility issues that must be considered when

designing application programs.

Many of the interfaces are the same as those used by the IBM Personal Computer AT. In most cases,

the command and status organization of these interfaces is maintained.

The functional interfaces are compatible with the following interfaces:

Ÿ Intel 8259 interrupt controllers (edge-triggered mode)

Ÿ National Semiconductor NS16450 and NS16550A serial communication controllers

Ÿ Motorola MC146818 Time of Day Clock command and status (CMOS reorganized)

Ÿ Intel 8254 timer, driven from a 1.193 MHz clock (channels 0, 1, and 2)

Ÿ Intel 8237 DMA controller, except for the Command and Request registers and the Rotate and Mask

functions; the Mode register is partially supported

Ÿ Intel 8272 or 82077 diskette drive controllers

Ÿ Intel 8042 keyboard controller at addresses hex 0060 and hex 0064

Ÿ All video standards using VGA, EGA, CGA, MDA, and Hercules modes

Ÿ Parallel printer ports (Parallel 1, Parallel 2, and Parallel 3) in compatibility mode

Use the above information to develop application programs. Whenever possible, use the BIOS as an

interface to hardware to provide maximum compatibility and portability of applications among systems.

Hardware interrupts

Hardware interrupts are level-sensitive for PCI interrupts. The interrupt controller clears its in-service

command is sent regardless of whether the incoming interrupt request to the controller is active or

inactive.

The interrupt-in-progress latch is readable at an I/O-address bit position. This latch is read during the

interrupt service routine and might be reset by the read operation or it might require an explicit reset.

Note: For performance and latency considerations, designers might want to limit the number of devices

sharing an interrupt level.

With level-sensitive interrupts, the interrupt controller requires that the interrupt request be inactive at the

time the EOI command is sent; otherwise, a new interrupt request will be detected. To avoid this, a

level-sensitive interrupt handler must clear the interrupt condition (usually by a read or write operation to

an I/O port on the device causing the interrupt). After processing the interrupt, the interrupt handler:

1. Clears the interrupt

2. Waits one I/O delay

 Copyright IBM Corp. September 1999

Chapter 6. System compatibility

3. Sends the EOI

4. Waits one I/O delay

5. Enables the interrupt through the Set Interrupt Enable Flag command

Hardware interrupt IRQ9 is defined as the replacement interrupt level for the cascade level IRQ2.

Program interrupt sharing is implemented on IRQ2, interrupt hex 0A. The following processing occurs to

maintain compatibility with the IRQ2 used by IBM Personal Computer products:

1. A device drives the interrupt request active on IRQ2 of the channel.

2. This interrupt request is mapped in hardware to IRQ9 input on the second interrupt controller.

3. When the interrupt occurs, the system microprocessor passes control to the IRQ9 (interrupt hex 71)

interrupt handler.

4. This interrupt handler performs an EOI command to the second interrupt controller and passes control

to the IRQ2 (interrupt hex 0A) interrupt handler.

5. This IRQ2 interrupt handler, when handling the interrupt, causes the device to reset the interrupt

request before performing an EOI command to the master interrupt controller that finishes servicing

the IRQ2 request.

Diskette drives and controller

The following figures show the reading, writing, and formatting capabilities of the diskette drive.

Figure 17. 3.5-inch diskette drive reading, writing, and formatting capabilities

Diskette drive type

1.44 MB drive

720 KB Mode

RWF

1.44 MB Mode

RWF

2.88 MB drive

RWF

Copy protection The following methods of copy protection might not work in systems using the 3.5-inch

1.44 MB diskette drive.

Ÿ Bypassing BIOS routines

– Data transfer rate: BIOS selects the proper data transfer rate for the media being used.

– Diskette parameter table: Copy protection, which creates its own diskette parameter table, might

not work in these drives.

Ÿ Diskette drive controls

– Rotational speed: The time between two events in a diskette drive is a function of the controller.

– Access time: Diskette BIOS routines must set the track-to-track access time for the different types

of media that are used in the drives.

– ‘Diskette change’ signal: Copy protection might not be able to reset this signal.

Ÿ Write-current control: Copy protection that uses write-current control does not work, because the

controller selects the proper write current for the media that is being used.

Hard disk drives and controller

Reading from and writing to the hard disk is initiated in the same way as in IBM Personal Computer

products; however, new functions are supported.

Chapter 6. System compatibility 23

Chapter 6. System compatibility

Software compatibility

To maintain software compatibility, the interrupt polling mechanism that is used by IBM Personal Computer

products is retained. Software that interfaces with the reset port for the IBM Personal Computer

positive-edge interrupt sharing (hex address 02Fx or 06Fx, where x is the interrupt level) does not create

interference.

Software interrupts

With the advent of software interrupt sharing, software interrupt routines must daisy chain interrupts. Each

routine must check the function value, and if it is not in the range of function calls for that routine, it must

transfer control to the next routine in the chain. Because software interrupts are initially pointed to

address 0:0 before daisy chaining, check for this case. If the next routine is pointed to address 0:0 and

the function call is out of range, the appropriate action is to set the carry flag and do a RET 2 to indicate

an error condition.

Machine-sensitive programs

Programs can select machine specific features, but they must first identify the machine and model type.

IBM has defined methods for uniquely determining the specific machine type. The machine model byte

can be found through Interrupt 15H, Return System Configuration Parameters function (AH)=C0H).

24 Technical Information Manual

Appendix A. Connector pin assignments

The following figures show the pin assignments for various system board connectors.

Monitor connector

Figure 18. Monitor port connector pin assignments

Signal

Red

I/O

Signal

I/O

Green

Blue

Monitor ID 2 - Not

used

Ground

Red ground

Blue ground

Ground

I/O

Green ground

+5 V, used by DDC2B

Monitor ID 0 - Not

used

DDC2B serial data

Horizontal sync

DDC2B clock

Vertical sync

I/O

Memory connectors

168

Figure 19 (Page 1 of 3). System Memory Connector Pin Assignments

x64 Non-Parity

VSS

x72 ECC

VSS

x64 Non-Parity

VSS

x72 ECC

VSS

DQ0

DQ1

DQ2

DQ3

VCC

DQ4

DQ5

DQ6

DQ7

DQ8

VSS

DQ32

DQ33

DQ34

DQ35

VCC

DQ32

DQ33

DQ34

DQ35

VCC

DQ1

DQ2

DQ3

VCC

DQ4

DQ36

DQ37

DQ38

DQ39

DQ40

VSS

DQ36

DQ37

DQ38

DQ39

DQ40

VSS

DQ5

DQ6

DQ7

DQ8

VSS

 Copyright IBM Corp. September 1999

Appendix A. Connector pin assignments

Figure 19 (Page 2 of 3). System Memory Connector Pin Assignments

x64 Non-Parity

DQ9

DQ10

DQ11

DQ12

DQ13

VCC

DQ14

DQ15

x72 ECC

DQ9

DQ10

DQ11

DQ12

DQ13

VCC

DQ14

DQ15

CB0

CB1

VSS

x64 Non-Parity

DQ41

DQ42

DQ43

DQ44

DQ45

VCC

DQ46

DQ47

x72 ECC

DQ41

DQ42

DQ43

DQ44

DQ45

VCC

DQ46

DQ47

CB4

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

CB5

VSS

VCC

/WE

VCC

/WE0

DQMB0

DQMB1

/S0

VCC

/CAS

DQMB4

DQMB5

VCC

/CAS

DQMB4

DQMB5

/S1

DQMB0

DQMB1

/S0

/RAS

VSS

/RAS

VSS

A10/AP

BA1

BA0

A11

VCC

CK0

VSS

VCC

CK0

VSS

VCC

CK1

VCC

CK1

A12

VSS

CKE0

VSS

CKE0

/S3

/S2

DQMB2

DQMB3

DQMB2

DQMB3

DQMB6

DQMB7

A13

DQMB6

DQMB7

A13

VCC

CB2

CB3

VSS

DQ16

CB6

CB7

VSS

DQ16

VSS

DQ48

VSS

DQ48

26 Technical Information Manual

Appendix A. Connector pin assignments

Figure 19 (Page 3 of 3). System Memory Connector Pin Assignments

x64 Non-Parity

DQ17

DQ18

DQ19

VCC

x72 ECC

DQ17

DQ18

DQ19

VCC

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

x64 Non-Parity

DQ49

DQ50

DQ51

VCC

x72 ECC

DQ49

DQ50

DQ51

VCC

DQ52

DQ20

DQ52

CKE1

VSS

DQ21

DQ22

DQ23

VSS

DQ21

DQ22

DQ23

VSS

DQ53

DQ54

DQ55

VSS

DQ53

DQ54

DQ55

VSS

DQ24

DQ25

DQ26

DQ27

VCC

DQ24

DQ25

DQ26

DQ27

VCC

DQ56

DQ57

DQ58

DQ59

VCC

DQ56

DQ57

DQ58

DQ59

VCC

DQ60

DQ61

DQ62

DQ63

VSS

DQ28

DQ29

DQ30

DQ31

VSS

DQ28

DQ29

DQ30

DQ31

VSS

DQ60

DQ61

DQ62

DQ63

VSS

CK2

CK3

SA0

SDA

SA1

SCL

SA2

VCC

Figure 20 (Page 1 of 3). System memory connector pin input/output

Signal Name

GND

I/O

N/A

I/O

Signal Name

GND

I/O

N/A

I/O

N/A

I/O

MD0

MD32

MD33

MD34

MD35

VDD

MD1

MD2

MD3

VDD

MD4

MD36

MD37

MD38

MD39

MD40

MD5

MD6

MD7

MD8 (PAR0)

Appendix A. Connector pin assignments 27

Appendix A. Connector pin assignments

Figure 20 (Page 2 of 3). System memory connector pin input/output

Signal Name

GND

MD9

MD10

MD11

MD12

MD13

VDD

MD14

MD15

I/O

N/A

I/O

N/A

I/O

N/A

Signal Name

GND

MD41

MD42

MD43

MD44

MD45

VDD

MD46

MD47

I/O

N/A

I/O

N/A

I/O

N/A

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

GND

VDD

WE#

DQMB0#

DQMB1#

S0#

VDD

CAS#

DQMB4#

S1#

OE0#

GND

RAS#

GND

N/A

A10/AP

A11

BA1

N/A

A11

N/A

VDD

CK1

CK0

A14

GND

OE2#

S2#

GND

CKE0

S3#

N/A

DQMB2#

DQMB3#

WE2#

VDD

DQMB6#

DQMB7#

A15

N/A

I/O

VDD

N/A

I/O

N/A

GND

28 Technical Information Manual

Appendix A. Connector pin assignments

Figure 20 (Page 3 of 3). System memory connector pin input/output

Signal Name

MD16

MD17

MD18

MD19

VDD

I/O

N/A

I/O

N/A

I/O

N/A

I/O

N/A

I/O

N/A

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

Signal Name

MD48

MD49

MD50

MD51

VDD

I/O

N/A

I/O

N/A

I/O

N/A

I/O

N/A

I/O

N/A

MD20

CKE1

VREF

(CKE1)*

GND

MD52

VREF

GND

MD21

MD22

MD23

GND

MD53

MD54

MD55

GND

MD24

MD25

MD26

MD27

VDD

MD56

MD57

MD58

MD59

VDD

MD28

MD29

MD30

MD31

GND

MD60

MD61

MD62

MD63

GND

CK2

CK3

N/A

SA0

SDA

SA1

SCL

SA0

VDD

N/A

VDD

N/A

PCI connectors

A62

B62

Figure 21. PCI bus connector

Figure 22 (Page 1 of 3). PCI connector pin assignments

Signal

I/O

Signal

I/O

TRST#

−12 V DC

Appendix A. Connector pin assignments 29

Appendix A. Connector pin assignments

Figure 22 (Page 2 of 3). PCI connector pin assignments

Signal

I/O

Signal

I/O

+12 V DC

TMS

TCK

Ground

TDI

TDO

+5 V DC

INTA#

+5 V DC

INTC#

INTB#

+5 V DC

INTD#

Reserved

+5 V DC (I/O)

Reserved

Ground

PRSNT1#

Reserved

PRSNT2

Ground

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

Ground

+3.3V AUX

RST#

Reserved

Ground

+5 V DC (I/O)

GNT#

CLK

Ground

I/O

REQ#

PCIPME

+5 V DC (I/O)

Address/Data 31

Address/Data 29

Ground

I/O

Address/Data 30

+3.3 V DC

Address/Data 28

Address/Data 26

Ground

Address/Data 27

Address/Data 25

+3.3 V DC

C/BE 3#

Address/Data 24

IDSEL

+3.3 V DC

Address/Data 22

Address/Data 20

Ground

I/O

Address/Data 23

Ground

Address/Data 21

Address/Data 19

+3.3 V DC

Address/Data 17

C/BE 2#

Address/Data 18

Address/Data 16

+3.3 V DC

FRAME#

Ground

IRDY#

TRDY#

+3.3 V DC

DEVSEL#

Ground

STOP#

+3.3 V DC

SDONE

LOCK#

PERR#

SBO#

+3.3 V DC

SERR#

Ground

+3.3 V DC

C/BE(1)#

+3.3 V DC

C/BE 1#

30 Technical Information Manual

Appendix A. Connector pin assignments

Figure 22 (Page 3 of 3). PCI connector pin assignments

Signal

I/O

Signal

I/O

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

Address/Data 14

Ground

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

Address/Data 14

Ground

Address/Data 12

Address/Data 10

Ground

Address/Data 12

Address/Data 10

Ground

Key

Address/Data 8

Address/Data 7

+3.3 V DC

Address/Data 5

Address/Data 3

Ground

Address/Data 8

Address/Data 7

+3.3 V DC

Address/Data 5

Address/Data 3

Ground

Address/Data 1

+5 V DC (I/O)

ACK64#

Address/Data 1

+5 V DC (I/O)

ACK64#

+5 V DC

IDE connectors

Figure 23 (Page 1 of 2). IDE connector pin assignments

Signal

I/O

Signal

I/O

RESET

Ground

I/O

Ground

I/O write

Data bus bit 7

Data bus bit 8

Data bus bit 6

Data bus bit 9

Data bus bit 5

Data bus bit 10

Data bus bit 4

Data bus bit 11

Data bus bit 3

Data bus bit 12

Data bus bit 2

Data bus bit 13

I/O read

Ground

I/O channel ready

ALE

Ground

IRQ

CS16#

SA1

PDIAG#

Appendix A. Connector pin assignments 31

Appendix A. Connector pin assignments

Figure 23 (Page 2 of 2). IDE connector pin assignments

Signal

I/O

Signal

SA0

I/O

Data bus bit 1

Data bus bit 14

Data bus bit 0

Data bus bit 15

Ground

SA2

CS0#

CS1

Active#

Ground

Key (Reserved)

Diskette drive connector

Figure 24. Diskette Drive Connector Pin Assignments

Signal

I/O

Signal

I/O

Drive 2 installed #

Not connected

Ground

High density select

Not connected

Data rate 0

Ground

Index#

Reserved

Ground

Motor enable 0#

Drive select 1#

Drive select 0#

Motor enable 1#

Direction in#

Step#

Ground

MSEN1

Ground

Write data#

Ground

Write enable#

Track0#

Ground

MSEN0

Write protect#

Read data#

Ground

Head 1 select#

Diskette change#

Data rate 1

Power supply connector

Figure 25 (Page 1 of 2). Power Supply Connector Pin Assignments

Signal Name

+3.3 V

Signal Name

+3.3 V

−12 V

Ground

+5 V

Ground

ON/OFF

Ground

Reserved

Ground

+5 V

Ground

PWR GOOD

32 Technical Information Manual

Appendix A. Connector pin assignments

Figure 25 (Page 2 of 2). Power Supply Connector Pin Assignments

Signal Name

+5 V AUX

+12 V

Signal Name

+5 V

Modem/Ring Wakeup and Wake on LAN connectors

Figure 26. J13 Modem/Ring Wakeup Connector Pin Assignments

Description

Internal Modem Wake Up on Ring

Ground

Figure 27. J22 Wake on LAN Connector Pin Assignments

Description

+5v AUX

Ground

Internal Wake on LAN

USB port connectors

Figure 28. USB Port Connector Pin Assignments

Signal

VCC

-Data

+Data

Ground

Mouse and keyboard port connectors

Figure 29 (Page 1 of 2). Mouse port connector pin assignments

Signal

Data

I/O

Signal

I/O

Reserved

+5 V DC

Ground

Appendix A. Connector pin assignments 33

Appendix A. Connector pin assignments

Figure 29 (Page 2 of 2). Mouse port connector pin assignments

Signal

I/O

Signal

I/O

Clock

I/O

Reserved

Figure 30. Keyboard port connector pin assignments

Signal

I/O

Signal

I/O

Keyboard data

Ground

Mouse data

+5 V DC

Keyboard clock

Mouse clock

Serial port connector

Figure 31. Serial Port Connector Pin Assignments

Signal

I/O

Signal

I/O

Data carrier detect

Transmit data#

Ground

Receive data#

Data terminal read

Data set ready

Clear to send

Request to send

Ring indicator

Parallel port connector

Figure 32 (Page 1 of 2). Parallel port connector pin assignments

Signal

I/O

Signal

I/O

STROBE#

Data bit 1

Data bit 3

Data bit 5

Data bit 7

BUSY

Data bit 0

Data bit 2

Data bit 4

Data bit 6

ACK#

SLCT

AUTO FD XT#

INIT#

ERROR#

SLCT IN#

Ground

34 Technical Information Manual

Appendix A. Connector pin assignments

Figure 32 (Page 2 of 2). Parallel port connector pin assignments

Signal

Ground

I/O

Signal

I/O

Ground

Appendix A. Connector pin assignments 35

Appendix B. System address maps

System memory map

The first 640 KB of system board RAM is mapped starting at address hex 0000000. A 256 byte area and

a 1 KB area of this RAM are reserved for BIOS data areas. Memory can be mapped differently if POST

detects an error.

Figure 33. System memory map

Address range (decimal)

0 K – 512 K

Address range (hex)

00000–7FFFF

Size

Description

512 KB

127 KB

1 KB

Conventional

512 K – 639 K

80000–9FBFF

Extended conventional

Extended BIOS data

639 K – 640 K

9FC00–9FFFF

A0000–BFFFF

640 K – 767 K

128 KB

Dynamic video memory

display cache

768 K – 800 K

800 K – 896 K

896 K – 1 MB

C0000 to C7FFF

C8000–DFFFF

E0000–FFFFF

32 KB

96 KB

128 KB

Video ROM BIOS

(shadowed)

PCI space, available to

adapter ROMs

System ROM BIOS (main

memory shadowed)

1 MB – 16 MB

100000–FFFFFF

1000000–FFF7FFFF

512 KB

15 MB

PCI Space

16 MB – 4095.872 MB

FFF80000 –FFFFFFFF

4079.5 MB MB

System ROM BIOS

PCI Space (positive decode)

Input/output address map

The following figure lists resource assignments for the I/O address map. Any addresses that are not

shown are reserved.

Figure 34 (Page 1 of 3). I/O address map

Address (Hex)

0000–000F

0010–001F

0020–0021

0022–003F

0022–002F

0040–0043

0044–00FF

0060

Size

Description

16 bytes

2 bytes

30 bytes

2 bytes

4 bytes

28 bytes

1 byte

DMA 1

General I/O Locations — available to PCI bus

Interrupt controller 1

General I/0 locations — available to PCI bus

SMC SIO index/data register

Counter/timer 1

General I/0 locations — available to PCI bus

Keyboard controller byte - reset IRQ

PIIX4, System port B

0061

1 byte

0064

1 byte

Keyboard controller, CMD/STAT byte

Enable NMI

0070, bit 7

0070, bits 6:0

0071

1 bit

Real time clock, address

1 byte

Real time clock, data

0072–007F

14 bytes

General I/O locations — available to PCI bus

Appendix B. System address maps

Figure 34 (Page 2 of 3). I/O address map

Address (Hex)

0080

Size

Description

1 byte

POST checkpoint register during POST only

008F

1 byte

Refresh page register

0080–008F

0090–0091

0092

16 bytes

15 bytes

1 byte

ICH1, DMA page registers

General I/O locations — available to PCI bus

PS/2 keyboard controller registers

0093–009F

00A0–00A1

00A2–00BF

00C0–00DF

00E0–00EF

00F0

15 bytes

2 bytes

30 bytes

31 bytes

16 bytes

1 byte

General I/O locations

Interrupt controller 2

APM control

DMA 2

General I/O locations — available to PCI bus

BX, Coprocessor Error Register

00F1–016F

0170–0177

01F0–01F7

0200–0207

0220–0227

0228–0277

0278–027F

0280–02E7

02E8–02EF

02F8–02FF

0338–033F

0340–036F

0372–0375

0376–0377

0378–037F

0380–03B3

03B4–03B7

03BA

127 bytes

8 bytes

80 bytes

8 bytes

102 bytes

8 bytes

48 bytes

4 bytes

2 bytes

8 bytes

52 bytes

4 bytes

1 byte

General I/O locations — available to PCI bus

Secondary IDE channel

Primary IDE channel

Available

SMC 37C673, Serial port 3 or 4

General I/O locations — available to PCI bus

SMC 27C673, LPT3

Available

SMC PC37C673, Serial port 3 or 4

COM2

SMC PC37C673, Serial port 3 or 4

Available

IDE channel 1 command

LPT2

Available

Video

03BC–03BE

03C0–03CF

03D4–03D7

03DA

16 bytes

4 bytes

1 byte

LPT1

Video

03D0–03DF

03E0–03E7

03E8–03EF

03F0–03F5

03F6

11 bytes

8 bytes

6 bytes

1 byte

Available

COM3 or COM4

Diskette channel 1

Primary IDE channel command port

Diskette channel 1 command

Diskette disk change channel

Primary IDE channel status port

COM1

03F7 (Write)

03F7, bit 7

03F7, bits 6:0

03F8–03FF

0400–047F

1 byte

1 bit

7 bits

8 bytes

128 bytes

Available

Appendix B. System address maps 37

Appendix B. System address maps

Figure 34 (Page 3 of 3). I/O address map

Address (Hex)

0480–048F

0490–0CF7

0CF8–0CFB

0CFC–0CFF

LPTn + 400h

0CF9

Size

Description

16 bytes

1912 bytes

4 bytes

DMA channel high page registers

Available

PCI Configuration address register

PCI Configuration data register

ECP port, LPTn base address + hex 400

Turbo and reset control register

Available

4 bytes

8 bytes

1 byte

0D00–FFFF

62207 bytes

DMA I/O address map

The following figure lists resource assignments for the DMA address map. Any addresses that are not

shown are reserved.

Figure 35 (Page 1 of 2). DMA I/O address map

Address (Hex)

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0081

0082

0083

0087

0089

008A

008B

008F

00C0

00C2

00C4

00C6

Description

Bits

Byte pointer

Yes

Channel 0, Memory Address register

Channel 0, Transfer Count register

Channel 1, Memory Address register

Channel 1, Transfer Count register

Channel 2, Memory Address register

Channel 2, Transfer Count register

Channel 3, Memory Address register

Channel 3, Transfer Count register

Channels 0–3, Read Status/Write Command register

Channels 0–3, Write Request register

Channels 0–3, Write Single Mask register bits

Channels 0–3, Mode register (write)

Channels 0–3, Clear byte pointer (write)

Channels 0–3, Master clear (write)/temp (read)

Channels 0–3, Clear Mask register (write)

Channels 0–3, Write All Mask register bits

00–15

00–07

00–02

00–07

N/A

Yes

00–07

00–03

00–07

00–15

Channel 2, Page Table Address register

Channel 3, Page Table Address register

Channel 1, Page Table Address register

Channel 0, Page Table Address register

Channel 6, Page Table Address register

Channel 7, Page Table Address register

Channel 5, Page Table Address register

Channel 4, Page Table Address/Refresh register

Channel 4, Memory Address register

Channel 4, Transfer Count register

Yes

Channel 5, Memory Address register

Channel 5, Transfer Count register

38 Technical Information Manual

Appendix B. System address maps

Figure 35 (Page 2 of 2). DMA I/O address map

Address (Hex)

00C8

Description

Bits

Byte pointer

Channel 6, Memory Address register

Channel 6, Transfer Count register

00–15

00–07

00–02

00–07

N/A

Yes

00CA

00CC

00CE

Channel 7, Memory Address register

Channel 7, Transfer Count register

00D0

Channels 4–7, Read Status/Write Command register

Channels 4–7, Write Request register

Channels 4–7, Write Single Mask register bit

Channels 4–7, Mode register (write)

Channels 4–7, Clear byte pointer (write)

Channels 4–7, Master clear (write)/temp (read)

Channels 4–7, Clear Mask register (write)

Channels 4–7, Write All Mask register bits

Channels 5–7, 8- or 16-bit mode select

00D2

00D4

00D6

00D8

00DA

00–07

00–03

00–07

00DC

00DE

00DF

PCI configuration space map

Bus number (hex)

Device number

(hex)

Function number

(hex)

Description

Intel 82810-DC 100 Host bridge

Intel 84440BX VGA graphics

Intel 82801 PCI–to–PCI bridge

Intel 82810 PCI–to–LPC bridge

IDE controller

USB

Intel 82801 SMBus

Audio multimedia

Upper byte of memory address register.

Appendix B. System address maps 39

Appendix C. IRQ and DMA channel assignments

The following figures list the interrupt request (IRQ) and direct memory access (DMA) channel

assignments.

Figure 36. IRQ channel assignments

IRQ

NMI

SMI

System resource

Critical system error

System management interrupt — power management

Reserved (interval timer)

Reserved (keyboard)

Reserved, Cascade interrupt from slave PIC

COM2 ³

COM1 ³

Available to user

Diskette controller

LPT1 ³

Real-time clock

ACPI BIOS

Audio

Video

Mouse port

Reserved (math coprocessor)

Primary IDE (if present)

Secondary IDE (if present)

Figure 37. DMA channel assignments

DMA channel

Data width

8 bits

System resource

Open

8 bits

Open

8 bits

Diskette drive

8 bits

Parallel port (for ECP or EPP)

–

Reserved (cascade channel)

16 bits

Open

Default, can be changed to another IRQ.

Appendix D. Error Codes

Appendix D. Error codes

A complete list of POST error codes is provided in PC 300GL User Guide and in Hardware Maintenance

Manual.

POST error codes

POST error messages appear when POST finds problems with the hardware during power-on or when a

change in the hardware configuration is found. POST error messages are 3-, 4-, 5-, 8-, or 12-character

alphanumeric messages.

POST beep codes

One beep and the appearance of text on the monitor indicate successful completion of POST. More than

one beep indcates that POST detected an error.

A complete list of beep codes is provided in Hardware Maintenance Manual.

Appendix E. Notices and trademarks

References in this publication to IBM products, programs, or services do not imply that IBM intends to

make these available in all countries in which IBM operates. Any reference to an IBM product, program,

or service is not intended to state or imply that only that IBM product, program, or service may be used.

Subject to IBM’s valid intellectual property or other legally protectable rights, any functionally equivalent

product, program, or service may be used instead of the IBM product, program, or service. The evaluation

and verification of operation in conjunction with other products, except those expressly designated by IBM,

are the responsibility of the user.

IBM may have patents or pending patent applications covering subject matter in this document. The

furnishing of this document does not give you any license to these patents. You can send license

inquiries, in writing, to:

IBM Director of Licensing

IBM Corporation

North Castle Drive

Armonk, NY 10504-1785

U.S.A.

Any references in this publication to non-IBM Web sites are provided for convenience only and do not in

any manner serve as an endorsement of those Web sites. The materials at those Web sites are not part

of the materials for this IBM product and use of those Web sites is at your own risk.

The following terms are trademarks of the IBM Corporation in the United States or other countries or both:

Alert on LAN

IBM

PC 300

PS/2

PC 100

Wake on LAN

Intel, Celeron, LANDesk, and MMX are trademarks of Intel Corporation in the United States, other

countries, or both.

Microsoft, Windows, OnNow, and Windows NT are trademarks of Microsoft Corporation in the United

States, other countries, or both.

Other company, product, and service names may be trademarks or service marks of others.

References

Ÿ Advanced Power Management (APM) BIOS

Interface Specification 1.2/

Ÿ PCI BIOS Specification 2.0

Source: PCI Special Interest Group

Source: Intel Corporation

Ÿ PCI Local Bus Specification 2.1

Ÿ AT Attachment Interface with Extensions

Source: American National Standard of Accredited

Standards Committee

Source: PCI Special Interest Group

Ÿ Plug and Play BIOS Specification 1.1

Source: Microsoft Corporation; available at

http://www.microsoft.com/hwdev

Ÿ Extended Capabilities Port: Specification Kit

Source: Microsoft Corporation

Ÿ Plug and Play BIOS Specification, Errata and

Clarifications 1.0

Ÿ Intel Microprocessor and Peripheral Component

Literature

Source: Microsoft Corporation

Source: Intel Corporation

Ÿ Universal Serial Bus Specifications

Source: http://www.usb.org

Ÿ Video Electronics Standards Association 1.2

Source: http://www.vesa.org

Ÿ AT24RF08A- PCID Specification

Ÿ Low Pin Count Interface Specification 1.1

Index

controller (continued)

serial 10

copy protection 23

ACPI 21

address map

DMA 38

I/O 36

system memory 36

advanced configuration and power interface 21

advanced power management 21

APM 21

diagnostic program 21

DIMM connectors

diskette drive

change signal 23

audio 10

compatibility 23

controller 10

write current 23

diskette drives 23

DMA (direct memory access) channel assignments 40

beep codes 41

BIOS 20

BIOS data areas 36

bus

IDE

environment, operating 15

error codes, POST 41

Ethernet port 12

LPC

PCI 4, 12

universal serial bus

bypassing BIOS 23

fault, overvoltage 19

flash EEPROM 12

flash update 21

frequency, input power 17

Celeron microprocessor with MMX technology

chip set 3, 10

clock, real-time 12

CMOS RAM 12

compatibility

Graphics memory controller hub

hardware 22

software 24

component maximum current 18

configuration/setup utility program 21

connector

hard disk drive

compatibility 23

controller 23

DIMM 25

diskette drive 32

IDE 31

keyboard/mouse ports 33

modem/ring wakeup 33

monitor 25

parallel port 34

PCI 29

hardware compatibility 22

hardware interrupts 22

I/O

controller 10

features 13

I/O address map 36

IDE interface

information, related vi

input power

power supply 32

serial ports 34

USB 33

Wake on LAN 33

controller

diskette drive 10, 23

I/O 10

keyboard/mouse 11

parallel 11

frequency 17

requirements 17

voltage 17

Index

interrupt request assignments 40

power (continued)

load currents 18

management modes 21

output protection 19

outputs 18

jumper

configuration 13

locations (system board) 13

protection, power supply 19

publications, related vi

L2 cache

RAM (random access memory) 36

random access memory (RAM) 36

references 43

level-sensitive interrupts 22

load currents 18

related information vi

reserved

areas vi

machine-sensitive programs 24

memory

error in 36

map, system 36

RAM 36

SDRAM (synchronous dynamic random access

memory)

system memory map 36

messages, POST error 41

microprocessor

serial port 10

short circuit 19

software

compatibility 24

interrupts 24

specifications 15, 16

mechanical 15

system

features

modes, power management 21

network support

memory maps 36

specifications 15

noise level 15, 16

ordering publications vi

outputs, power supply 18

overvoltage fault 19

token ring port 12

universal serial bus

connectors 33

parallel port 11

PCI

port

technology

bus

connectors 12

Plug and Play 20

polling mechanism 24

port

video

subsystem

ethernet 12

keyboard/mouse 11

parallel 11

voltage, input power 17

voltage, output power 17

serial 10

POST 20, 36

POST error codes 41

power

Wake on LAN

Wake Up on Ring

consumption 21

description 17

for components 18

write current, diskette 23

Index 45

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