SSI America Power Supply EPS2U User Manual

SSI  
EPS2U  
Power Supply Design Guide  
A Server System Infrastructure (SSI) Specification  
For Entry Chassis Power Supplies  
Revision 2.1  
Revision History  
Orig./Rev.  
Description of Changes  
Date  
1.0  
1.1  
Initial release of EPS2U specification  
Updated EPS2U spec with an added 12V 240VA channel, updated mounting  
features, and added gold comment for gold signal contacts  
4/14/02  
1.2  
2.0  
Approved EPS2U specification including changes from 4/23/2002 SSI council meeting  
4/23/02  
9/27/02  
Added output power level recommendations for 550W, 600W, and 650W power  
supplies and updated connector pin-outs.  
Modified 12V continuous and peak requirements for 480W power level.  
Updated transient load requirements, 240VA requirements, and signal description for  
PWOK.  
Removed temperature rise requirements from thermal section and added efficiency  
and airflow recommendations for each power level.  
Section 4.2 - Changed operating temperature to 45°C from 50°C  
Section 6.1 - Added 3.3V remote sense to pin 1 of baseboard connector  
Section 6.1 - Changed +12V4 wire color to Yellow/Green stripe  
Added Section 6.1.1 – 12V Power Rail Configurations  
2.1  
5/16/03  
Section 6.4 - Changed output load rating tables  
Defined one load range per output level (vs. two)  
Increased +12V currents for 550, 600 & 650W split plane supplies  
Section 6.6 - Adjusted transient load requirements  
 
SSI  
EPS2U Power Supply Design Guide, V2.1  
Contents  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
Figures  
Tables  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
1 Purpose  
This 2U Rack Power Supply Specification defines a common power supply used in entry-level servers. This  
supply may range typically from 400 to 700 watts and is used in a non-redundant configuration. The scope of this  
document defines the requirements for one supply in this power range. The parameters of this supply are defined  
in this specification for open industry use.  
This specification defines 480W, 550W, 600W, and 650W power supplies with multiple outputs; 3.3 V, 5 V, 12V, -  
12 V, and 5 VSB. Because of its connector leads, the power supply is not intended to be a hot swap type of  
power supply.  
2 Conceptual Overview  
In the Entry server market, the bulk power system must source power on several output rails.  
These rails are typically as follows:  
+3.3 V  
+5 V  
+12 V  
–12 V  
5 V standby  
NOTE  
Local DC-DC converters shall be utilized for processor power, and will ideally convert power from the +12 V  
rail, however, they may also convert power from other rails.  
The bulk power system may be a n+1 redundant power system or a non-redundant power system.  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
3 Definitions/Terms/Acronyms  
Required  
The status given to items within this design guide, which are required to  
meet SSI guidelines and a large majority of system applications.  
Recommended  
Optional  
The status given to items within this design guide which are not required to  
meet SSI guidelines, however, are required by many system applications.  
The status given to items within this design guide, which are not required to  
meet SSI guidelines, however, some system applications may optionally  
use these features.  
Autoranging  
A power supply that automatically senses and adjusts itself to the proper  
input voltage range (110 VAC or 220 VAC). No manual switches or  
manual adjustments are needed.  
CFM  
Cubic Feet per Minute (airflow).  
Dropout  
A condition that allows the line voltage input to the power supply to drop to  
below the minimum operating voltage.  
Latch Off  
A power supply, after detecting a fault condition, shuts itself off. Even if the  
fault condition disappears, the supply does not restart unless manual or  
electronic intervention occurs. Manual intervention commonly includes  
briefly removing and then reconnecting the supply, or it could be done  
through a switch. Electronic intervention could be done by electronic  
signals in the Server System.  
Monotonically  
A waveform changes from one level to another in a steady fashion, without  
intermediate retracement or oscillation.  
Noise  
The periodic or random signals over frequency band of 0 Hz to 20 MHz.  
Overcurrent  
A condition in which a supply attempts to provide more output current than  
the amount for which it is rated. This commonly occurs if there is a "short  
circuit" condition in the load attached to the supply.  
PFC  
Power Factor Corrected.  
Ripple  
Rise Time  
The periodic or random signals over a frequency band of 0 Hz to 20 MHz.  
Rise time is defined as the time it takes any output voltage to rise from  
10% to 95% of its nominal voltage.  
Sag  
The condition where the AC line voltage drops below the nominal voltage  
conditions.  
Surge  
The condition where the AC line voltage rises above nominal voltage.  
VSB or Standby Voltage  
An output voltage that is present whenever AC power is applied to the AC  
inputs of the supply.  
MTBF  
Mean time between failure.  
PWOK  
A typical logic level output signal provided by the supply that signals the  
Server System that all DC output voltages are within their specified range.  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
4 Mechanical Overview  
STATUS  
Required (Optional)  
Note: Some enclosure features are noted as optional in the drawing below. These features may be use in some  
chassis designs where only top access is allowed for the cage mounting.  
The EPS2U is a power supply enclosure intended to handle a power range of 400W to 700W. A mechanical  
drawing of the power supply cage is shown below in Figure 1.  
Optional mounting features for top access  
mounting of the power supply.  
Allow for 1.2mm  
protrusion (x4)  
Figure 1: Enclosure Drawing  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
4.1 Airflow Requirements  
STATUS  
Recommended  
The power supply shall have a two-speed fan(s) and provide cooling to both the supply and the system. During  
low-speed fan operation, the power supply must not exceed a noise level of 43 dBa measured at one meter on all  
faces. At low fan speed, the power supply shall provide a minimum of 12 CFM of airflow with 0.003 inH2O of  
system backpressure. At high fan speed, the power supply shall provide a minimum of 20 CFM with 0.006 inH2O  
of system backpressure.  
4.2 Temperature Requirements  
STATUS  
Recommended  
The power supply shall operate within all specified limits over the Top temperature range. The average air  
temperature difference (Tps ) from the inlet to the outlet of the power supply shall not exceed the values shown  
below in Table 1. All airflow shall pass through the power supply and not over the exterior surfaces of the power  
supply.  
Table 1: Thermal Requirements  
ITEM  
DESCRIPTION  
MIN  
MAX  
UNITS  
Operating temperature range.  
0
50  
°C  
Top  
Non-operating temperature range.  
-40  
70  
°C  
Tnon-op  
The power supply must meet UL enclosure requirements for temperature rise limits. All sides of the power supply  
with exception of the air exhaust side, must be classified as “Handle, knobs, grips, etc. held for short periods of  
time only”.  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
5 AC Input Requirements  
STATUS  
Required  
The power supply shall incorporate universal power input with active power factor correction, which shall reduce  
line harmonics in accordance with the EN61000-3-2 and JEIDA MITI standards.  
5.1 AC Inlet Connector  
STATUS  
Required  
The AC input connector shall be an IEC 320 C-14 power inlet. This inlet is rated for 15 A/250 VAC.  
5.2 AC Input Voltage Specification  
STATUS  
Required  
The power supply must operate within all specified limits over the following input voltage range. Harmonic  
distortion of up to 10% THD must not cause the power supply to go out of specified limits. The power supply shall  
operate properly at 85 VAC input voltage to guarantee proper design margins.  
Table 2: AC Input Rating  
PARAMETER MIN  
RATED  
MAX  
Voltage (110)  
Voltage (220)  
Frequency  
90 Vrms  
100-127 Vrms  
140 Vrms  
180 Vrms 200-240 Vrms  
47 Hz  
264 Vrms  
63 Hz  
5.3 Efficiency  
STATUS  
Recommended  
The following efficiency requirements are provided as a recommendation to allow for proper power supply cooling  
when installed in a system.  
Table 3: Efficiency  
Power Level  
480W  
Efficiency  
68%  
Airflow (reference)  
20 CFM  
550W  
68%  
20 CFM  
600W  
72%  
20 CFM  
650W  
72%  
20 CFM  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
5.4 AC Line Dropout  
STATUS  
Required  
An AC line dropout is defined to be when the AC input drops to 0 VAC at any phase of the AC line for any length  
of time. During an AC dropout of one cycle or less the power supply must meet dynamic voltage regulation  
requirements over the rated load. An AC line dropout of one cycle or less shall not cause any tripping of control  
signals or protection circuits. If the AC dropout lasts longer than one cycle, the power supply should recover and  
meet all turn on requirements. The power supply must meet the AC dropout requirement over rated AC voltages,  
frequencies, and output loading conditions. Any dropout of the AC line shall not cause damage to the power  
supply.  
5.5 AC Line Fuse  
STATUS  
Required  
The power supply shall incorporate one input fuse on the LINE side for input over-current protection to prevent  
damage to the power supply and meet product safety requirements. Fuses should be slow blow type or  
equivalent to prevent nuisance trips. AC inrush current shall not cause the AC line fuse to blow under any  
conditions. All protection circuits in the power supply shall not cause the AC fuse to blow unless a component in  
the power supply has failed. This includes DC output load short conditions.  
5.6 AC Inrush  
STATUS  
Required  
The power supply must meet inrush requirements for any rated AC voltage, during turn on at any phase of AC  
voltage, during a single cycle AC dropout condition, during repetitive ON/OFF cycling of AC, and over the  
specified temperature range (Top). The peak inrush current shall be less than the ratings of its critical components  
(including input fuse, bulk rectifiers, and surge limiting device).  
STATUS  
Recommended  
An additional inrush current limit is recommended for some system applications that require multiple systems on a  
single AC circuit. AC line inrush current shall not exceed 40 A peak for one-quarter of the AC cycle, after which,  
the input current should be no more than the specified maximum input current from Table 2.  
5.7 AC Line Transient Specification  
STATUS  
Recommended  
AC line transient conditions shall be defined as “sag” and “surge” conditions. Sag conditions (also referred to as  
“brownout” conditions) will be defined as the AC line voltage dropping below nominal voltage. Surge conditions  
will be defined as the AC line voltage rising above nominal voltage.  
The power supply shall meet the requirements under the following AC line sag and surge conditions.  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
Table 4: AC Line Sag Transient Performance  
AC Line Sag  
Duration  
Sag  
Operating AC Voltage  
Line Frequency  
Performance Criteria  
Continuous  
10%  
Nominal AC Voltage ranges  
50/60 Hz  
50/60 Hz  
No loss of function or performance  
No loss of function or performance  
0 to 1 AC  
cycle  
100% Nominal AC Voltage ranges  
>1 AC cycle  
>10% Nominal AC Voltage ranges  
50/60 Hz  
Loss of function acceptable, self  
recoverable  
Table 5: AC Line Surge Transient Performance  
AC Line Surge  
Duration  
Surge Operating AC Voltage  
Line Frequency  
Performance Criteria  
Continuous  
10%  
30%  
Nominal AC Voltages  
50/60 Hz  
No loss of function or performance  
No loss of function or performance  
0 to ½ AC  
cycle  
Mid-point of nominal AC  
Voltages  
50/60 Hz  
5.8 AC Line Fast Transient Specification  
STATUS  
Recommended  
The power supply shall meet the EN61000-4-5 directive and any additional requirements in IEC1000-4-5:1995  
and the Level 3 requirements for surge-withstand capability, with the following conditions and exceptions:  
These input transients must not cause any out-of-regulation conditions, such as overshoot and  
undershoot, nor must it cause any nuisance trips of any of the power supply protection circuits.  
The surge-withstand test must not produce damage to the power supply.  
The supply must meet surge-withstand test conditions under maximum and minimum DC-output load  
conditions.  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
6 DC Output Specification  
6.1 Output Connectors  
The power supply shall have one of the two following output connector and wire harness configurations,  
depending upon the type of 12V rail configuration needed by the system.  
6.1.1 12V Power Rail Configurations  
There are two types of 12V rail configurations for systems: ‘Common plane’ and ‘split plane’ processor power  
delivery. The ‘common plane’ system has both processors powered from a single 12V rail (+12V1) from the  
power supply. The ‘split plane’ system has both processors powered from separate 12V rails (+12V1 and  
+12V2), one dedicated to each processor. The system, in both cases, has an additional 12V rail to power the rest  
of the baseboard +12V loads and dc/dc converters. +12V1, +12V2, and +12V3 should not be connected together  
on the baseboard to ensure that 240VA protection circuits in the power supply operate properly.  
Table 6: 12V Rail Summary  
Common Plane System  
Split Plane System  
+12V1  
+12V2  
Processors  
+12V1  
Processor 1  
Baseboard components other +12V2  
than processors  
Processor 2  
+12V3  
Drives and peripherals  
+12V3  
Baseboard components other than  
processors  
+12V4  
Drives and peripherals  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
6.1.2 Baseboard power connector  
STATUS  
Required  
Connector housing: 24-Pin Molex 39-01-2240 or equivalent  
Contact: Molex 44476-1111 or equivalent  
Table 7: P1 Baseboard Power Connector – Common Plane  
Pin  
Signal  
18 AWG Color  
Pin  
Signal  
18 AWG Color  
1
+3.3 VDC,  
3.3RS 1  
Orange,  
Orange/white stripe  
13  
+3.3 VDC  
Orange  
2
+3.3 VDC  
COM  
Orange  
Black  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
-12 VDC  
COM  
Blue  
3
Black  
Green  
Black  
Black  
Black  
N.C.  
4
+5 VDC  
COM  
Red  
PS_ON  
COM  
5
Black  
6
+5 VDC  
COM  
Red  
COM  
7
Black  
COM  
8
PWR OK  
5 VSB  
Gray  
Reserved (-5 V in ATX)  
+5 VDC  
+5 VDC  
+5 VDC  
COM  
9
Purple  
Red  
10  
11  
12  
+12 V2  
+12 V2  
+3.3 VDC  
Yellow/Blue Stripe  
Yellow/Blue Stripe  
Orange  
Red  
Red  
Black  
Table 8: P1 Baseboard Power Connector – Split Plane  
Pin  
Signal  
18 AWG Color  
Pin  
Signal  
18 AWG Color  
1
Orange,  
Orange/white stripe  
13  
+3.3 VDC  
Orange  
+3.3 VDC,  
3.3RS 1  
2
+3.3 VDC  
COM  
Orange  
Black  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
-12 VDC  
COM  
Blue  
3
Black  
Green  
Black  
Black  
Black  
N.C.  
4
+5 VDC  
COM  
Red  
PS_ON  
COM  
5
Black  
6
+5 VDC  
COM  
Red  
COM  
7
Black  
COM  
8
PWR OK  
5 VSB  
Gray  
Reserved (-5 V in ATX)  
+5 VDC  
+5 VDC  
+5 VDC  
COM  
9
Purple  
Red  
10  
11  
12  
+12 V3  
+12 V3  
+3.3 VDC  
Yellow/Blue Stripe  
Yellow/Blue Stripe  
Orange  
Red  
Red  
Black  
1. 3.3V remote sense signal double crimped with 3.3V contact.  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
2. If 240VA limiting is not a requirement for the power supply than all +12V outputs are common and may have the same  
wire color (yellow).  
6.1.3 Processor Power Connector  
STATUS  
Required  
Connector housing: 8-Pin Molex 39-01-2080 or equivalent  
Contact: Molex 44476-1111 or equivalent  
Table 9: Processor Power Connector – Common Plane  
Pin  
Signal  
18 AWG color  
Pin  
Signal  
18 AWG Color  
1
COM  
Black  
5
+12 V1  
Yellow/Black Stripe  
2
3
4
COM  
COM  
COM  
Black  
Black  
Black  
6
7
8
+12 V1  
+12 V1  
+12 V1  
Yellow/Black Stripe  
Yellow/Black Stripe  
Yellow/Black Stripe  
Table 10: Processor Power Connector – Split Plane  
Pin  
Signal  
18 AWG color  
Pin  
Signal  
18 AWG Color  
1
COM  
Black  
5
+12 V1  
Yellow/Black Stripe  
2
3
4
COM  
COM  
COM  
Black  
Black  
Black  
6
7
8
+12 V1  
+12 V2  
+12 V2  
Yellow/Black Stripe  
Yellow  
Yellow  
If 240VA limiting is not a requirement for the power supply than all +12V outputs are common and may have the same wire  
color (yellow).  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
6.1.4 Peripheral Power Connectors  
STATUS  
Required  
Connector housing: Amp 1-480424-0 or equivalent  
Contact: Amp 61314-1 contact or equivalent  
Table 11: Peripheral Power Connectors  
Pin Signal  
18 AWG Color  
1
2
3
4
+12V2 (+12V3 or +12V4) 1, 2  
Yellow (Yellow/Blue Stripe or Yellow/Green stripe) 1, 2  
COM  
Black  
Black  
Red  
COM  
+5 VDC  
1. The +12V power to peripherals may be split between the second, third, or fourth +12V channel for the purpose of  
limiting power to less than 240VA.  
2. If 240VA limiting is not a requirement for the power supply than all +12V outputs are common and may have the  
same wire color.  
6.1.5 Floppy Power Connector  
STATUS  
Required  
Connector housing: Amp 171822-4 or equivalent  
Table 12: P9 Floppy Power Connector  
Pin Signal  
22 AWG Color  
1
2
3
4
+5 VDC  
Red  
COM  
Black  
COM  
Black  
+12V2 (+12V3 or +12V4) 1, 2  
Yellow (Yellow/Blue Stripe or Yellow/Green stripe) 1, 2  
1. The +12V power to peripherals may be split between the second, third, or fourth +12V channel for the purpose of  
limiting power to less than 240VA.  
2. If 240VA limiting is not a requirement for the power supply than all +12V outputs are common and may have the same  
wire color.  
6.1.6 Server Signal Connector  
STATUS  
Optional  
For server systems with SMBus features, the power supply may have an additional connector, which provides  
serial SMBus for FRU data and remote sense on 3.3V and Return.  
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EPS2U Power Supply Design Guide, V2.1  
If the optional server signal connector is not used on the power supply or the connector is unplugged, the power  
supply shall utilize the 3.3RS on the baseboard connector (Pin 1).  
Connector housing: 5-pin Molex 50-57-9405 or equivalent  
Contacts: Molex 16-02-0088 or equivalent (gold plated)  
Table 13: Server Signal Connector  
Pin  
Signal  
24 AWG Color  
1
I2C Clock  
White/Green Stripe  
2
3
4
5
I2C Data  
Reserved  
ReturnS  
3.3RS  
White/Yellow Stripe  
NA  
Black/White Stripe  
Orange/White Stripe  
6.2 Grounding  
STATUS  
Required  
The ground of the pins of the power supply wire harness provides the power return path. The wire harness  
ground pins shall be connected to safety ground (power supply enclosure).  
6.3 Remote Sense  
STATUS  
Optional  
The power supply may have remote sense for the +3.3V (3.3VS) and return (ReturnS) if the Optional Server  
Signal connector is implemented. The remote sense return (ReturnS) is used to regulate out ground drops for all  
output voltages; +3.3V, +5 V, +12V1, +12V2, +12V3, -12 V, and 5 VSB. The 3.3V remote sense (3.3VS) is used  
to regulate out drops in the system for the +3.3 V output. The remote sense input impedance to the power supply  
must be greater than 200 W on 3.3 VS and ReturnS. This is the value of the resistor connecting the remote  
sense to the output voltage internal to the power supply. Remote sense must be able to regulate out a minimum  
of 200 mV drop on the +3.3 V output. The remote sense return (ReturnS) must be able to regulate out a minimum  
of 200 mV drop in the power ground return. The current in any remote sense line shall be less than 5 mA to  
prevent voltage sensing errors. The power supply must operate within specification over the full range of voltage  
drops from the power supply’s output connector to the remote sense points.  
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SSI  
EPS2U Power Supply Design Guide, V2.1  
6.4 Output Power/Currents  
STATUS  
Recommended  
The following tables define the power and current ratings for 480 W, 550 W, 600 W, and 650 W power supplies.  
The combined output power of all outputs shall not exceed the rated output power. The power supply must meet  
both static and dynamic voltage regulation requirements for the minimum loading conditions.  
Table 14: 480 W Load Ratings – Common Plane  
Voltage  
Minimum Continuous  
Maximum Continuous Peak  
+3.3 V  
0.8 A  
24 A  
+5 V  
0.5 A  
0 A  
20 A  
+12V1 (Processors)  
+12V2 (Baseboard)  
-12 V  
18 A  
18 A  
0.5 A  
2.0 A  
22 A 7  
1.0 A  
0 A  
+5 VSB  
0.1 A  
1. Maximum continuous total DC output power should not exceed 480 W.  
2. Maximum continuous combined load on +3.3 VDC and +5 VDC outputs shall not exceed 115 W.  
3. Maximum Peak total DC output power should not exceed 550 W.  
4. Peak power and current loading shall be supported for a minimum of 1 second.  
5. Maximum combined current for the 12 V outputs shall be 32 A.  
6. Maximum 12V combined peak current shall be 44A.  
7. Peak +12 V1 current shall be supported for a minimum of 0.5 seconds.  
Table 15: 550 W Load Ratings – Split Plane  
Voltage  
Minimum Continuous  
Maximum Continuous  
Peak  
+3.3 V  
0.8 A  
24 A  
+5 V  
0.5 A  
0 A  
20 A  
+12V1  
+12V2  
+12V3  
+12V4  
-12 V  
10.5 A  
10.5 A  
14 A  
12 A  
12 A  
0 A  
0.9 A  
0.1 A  
0 A  
8.0 A  
0.5 A  
2.0 A  
13 A  
+5 VSB  
0.1 A  
1. Maximum continuous total DC output power should not exceed 550 W.  
2. Maximum continuous combined load on +3.3 VDC and +5 VDC outputs shall not exceed 140 W.  
3. Maximum peak total DC output power should not exceed 630 W.  
4. Peak power and current loading shall be supported for a minimum of 1 second.  
5. Maximum combined current for the 12 V outputs shall be 38 A.  
6. Peak current for the combined 12 V outputs shall be 45 A.  
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EPS2U Power Supply Design Guide, V2.1  
Table 16: 600 W Load Ratings – Split Plane  
Voltage  
Minimum Continuous  
Maximum Continuous  
Peak  
+3.3 V  
0.8 A  
24 A  
+5 V  
0.5 A  
0 A  
20 A  
12 A  
12 A  
14 A  
8.0 A  
0.5 A  
2.0 A  
+12V1  
+12V2  
+12V3  
+12V4  
-12 V  
15 A  
15 A  
0 A  
0.9 A  
0.1 A  
0 A  
13 A  
+5 VSB  
0.1 A  
1. Maximum continuous total DC output power should not exceed 600 W.  
2. Maximum continuous combined load on +3.3 VDC and +5 VDC outputs shall not exceed 140 W.  
3. Maximum peak total DC output power should not exceed 710 W.  
4. Peak power and current loading shall be supported for a minimum of 1 second.  
5. Maximum combined current for the 12 V outputs shall be 42 A.  
6. Peak current for the combined 12 V outputs shall be 51 A.  
Table 17: 650 W Load Ratings – Split Plane  
Voltage  
Minimum Continuous  
Maximum Continuous  
Peak  
+3.3 V  
0.8 A  
24 A  
+5 V  
0.5 A  
0 A  
24 A  
+12V1  
+12V2  
+12V3  
+12V4  
-12 V  
12.5 A  
12.5 A  
14 A  
15 A  
15 A  
0 A  
0.9 A  
0.1 A  
0 A  
8.0 A  
0.5 A  
2.0 A  
13 A  
+5 VSB  
0.1 A  
1. Maximum continuous total DC output power should not exceed 650 W.  
2. Maximum continuous combined load on +3.3 VDC and +5 VDC outputs shall not exceed 140 W.  
3. Maximum peak total DC output power should not exceed 770 W.  
4. Peak power and current loading shall be supported for a minimum of 1 second.  
5. Maximum combined current for the 12 V outputs shall be 45 A.  
6. Peak current for the combined 12 V outputs shall be 54 A.  
6.4.1 Standby Outputs  
STATUS  
Required  
The 5 VSB output shall be present when an AC input greater than the power supply turn on voltage is applied.  
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EPS2U Power Supply Design Guide, V2.1  
6.5 Voltage Regulation  
STATUS  
Required  
The power supply output voltages must stay within the following voltage limits when operating at steady state and  
dynamic loading conditions. These limits include the peak-peak ripple/noise specified in Section 5.8. All outputs  
are measured with reference to the return remote sense (ReturnS) signal. The 5 V, 12V1, 12V2, 12V3, –12 V and  
5 VSB outputs are measured at the power supply connectors referenced to ReturnS. The +3.3 V is measured at  
its remote sense signal (3.3VS) located at the signal connector.  
Table 18: Voltage Regulation Limits  
Parameter  
MIN  
NOM  
MAX  
Units  
Tolerance  
+3.3 V  
+3.20  
+3.30  
+3.46  
Vrms  
+5/-3%  
+5 V  
+4.80  
+5.00  
+5.25  
Vrms  
Vrms  
Vrms  
Vrms  
Vrms  
Vrms  
+5/-4%  
+5/-4%  
+5/-4%  
+5/-4%  
+9/-5%  
+5/-3%  
+12V1  
+12V2  
+12V3  
-12 V  
+11.52  
+11.52  
+11.52  
-11.40  
+4.85  
+12.00  
+12.00  
+12.00  
-12.20  
+5.00  
+12.60  
+12.60  
+12.60  
-13.08  
+5.25  
+5 VSB  
STATUS  
Optional  
Some system applications may require tighter regulation limits on the +5 V output. The optional regulation limits  
are shown below.  
Table 19: Optional +5V Regulation Limits  
Parameter  
MIN  
NOM  
MAX  
Units  
Tolerance  
+5 V  
+4.85  
+5.00  
+5.25  
Vrms  
+5/-3%  
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EPS2U Power Supply Design Guide, V2.1  
6.6 Dynamic Loading  
STATUS  
Required  
The output voltages shall remain within the limits specified in Table 18 for the step loading and within the limits  
specified in Table 20 for the capacitive loading. The load transient repetition rate shall be tested between 50 Hz  
and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification.  
The step load may occur anywhere within the MIN load to the MAX load shown in Table 14, Table 15, Table 16,  
Table 20: Transient Load Requirements  
Output  
Load Slew  
Rate  
Capacitive Load  
Step Load Size  
+3.3 V  
30% of max load  
30% of max load  
65% of max load  
25% of max load  
0.5 A/µs  
0.5 A/µs  
0.5 A/µs  
0.5 A/µs  
1000 µF  
1000 µF  
2200 µF  
1 µF  
+5 V  
12V1+12V2+12V3+12V4  
+5 VSB  
6.7 Capacitive Loading  
STATUS  
Required  
The power supply shall be stable and meet all requirements with the following capacitive loading ranges.  
Note: Up to 10,000 µF of the +12V capacitive loading may be on the +12V1 output.  
Table 21: Capacitve Loading Conditions  
Output  
MIN  
MAX  
Units  
+3.3 V  
10  
12,000  
µF  
+5 V  
10  
10  
1
12,000  
11,000  
350  
µF  
µF  
µF  
µF  
+12 V  
-12 V  
+5 VSB  
1
350  
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EPS2U Power Supply Design Guide, V2.1  
6.8 Ripple / Noise  
STATUS  
Required  
The maximum allowed ripple/noise output of the power supply is defined in Table 22. This is measured over a  
bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A 10 µF tantalum capacitor in parallel with a  
0.1 µF ceramic capacitor are placed at the point of measurement.  
Table 22: Ripple and Noise  
+3.3 V  
+5 V  
+12 V  
-12 V  
+5 VSB  
50 mVp-p  
50 mVp-p  
120 mVp-p  
120 mVp-p  
50 mVp-p  
6.9 Timing Requirements  
STATUS  
Required  
These are the timing requirements for the power supply operation. The output voltages must rise from 10% to  
within regulation limits (Tvout_rise) within 5 to 70 ms. The +3.3 V, +5 V and +12 V output voltages should start to  
rise at about the same time. All outputs must rise monotonically. The +5 V output needs to be greater than the  
+3.3 V output during any point of the voltage rise. The +5V output must never be greater than the +3.3V output  
by more than 2.25 V. Each output voltage shall reach regulation within 50 ms (Tvout_on) of each other during turn  
on of the power supply. Each output voltage shall fall out of regulation within 400 ms (Tvout_off) of each other  
during turn off. Figure 2 and Figure 3 show the turn ON and turn OFF timing requirements. In Figure 3, the  
timing is shown with both AC and PSON# controlling the ON/OFF of the power supply.  
Table 23: Output Voltage Timing  
Item  
Description  
MIN  
MAX  
Units  
Tvout_rise  
Output voltage rise time from each main output.  
5
70  
ms  
Tvout_on  
All main outputs must be within regulation of each  
other within this time.  
50  
ms  
Tvout_off  
All main outputs must leave regulation within this  
time.  
400  
ms  
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EPS2U Power Supply Design Guide, V2.1  
Vout  
10% Vout  
V1  
V2  
V3  
V4  
Tvout_off  
Tvout_rise  
Tvout_on  
Figure 2: Output Voltage Timing  
Table 24: Turn On/Off Timing  
Item  
Description  
MIN  
MAX  
UNITS  
Tsb_on_delay  
Delay from AC being applied to 5 VSB being  
within regulation.  
1500  
ms  
T ac_on_delay  
Tvout_holdup  
Delay from AC being applied to all output voltages  
being within regulation.  
2500  
ms  
ms  
Time all output voltages stay within regulation  
after loss of AC.  
18  
Tpwok_holdup  
Delay from loss of AC to deassertion of PWOK.  
17  
5
ms  
ms  
Tpson_on_delay  
Delay from PSON# active to output voltages within  
regulation limits.  
400  
50  
T pson_pwok  
Tpwok_on  
Delay from PSON# deactive to PWOK being  
deasserted.  
ms  
ms  
ms  
Delay from output voltages within regulation limits  
to PWOK asserted at turn on.  
100  
1
1000  
T pwok_off  
Delay from PWOK deasserted to output voltages  
(3.3 V, 5 V, 12 V, -12 V) dropping out of regulation  
limits.  
Tpwok_low  
Duration of PWOK being in the deasserted state  
during an off/on cycle using AC or the PSON#  
signal.  
100  
50  
ms  
ms  
Tsb_vout  
Delay from 5 VSB being in regulation to O/Ps  
being in regulation at AC turn on.  
1000  
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EPS2U Power Supply Design Guide, V2.1  
STATUS  
Recommended  
Item  
Description  
MIN  
MAX  
UNITS  
Tvout_holdup  
Time all output voltages stay within regulation  
after loss of AC.  
21  
ms  
Tpwok_holdup  
Tsb_holdup  
Delay from loss of AC to deassertion of PWOK.  
20  
70  
ms  
ms  
Time 5VSB output voltage stays within regulation  
after loss of AC.  
AC Input  
Tvout_holdup  
Vout  
TAC_on_delay  
Tpwok_low  
Tpwok_off  
Tpwok_on  
Tpwok_off  
Tsb_on_delay  
Tsb  
on delay  
Tpwok_on  
Tpwok_holdup  
Tpson_pwok  
PWOK  
Tsb_holdup  
5VSB  
Tsb_vout  
Tpson_on_delay  
PSON#  
AC turn on/off cycle  
PSON turn on/off cycle  
Figure 3: Turn On/Off Timing (Single Power Supply)  
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EPS2U Power Supply Design Guide, V2.1  
7 Protection Circuits  
STATUS  
Required  
Protection circuits inside the power supply shall cause only the power supply’s main outputs to shutdown. If the  
power supply latches off due to a protection circuit tripping, an AC cycle OFF for 15 s and a PSON# cycle HIGH  
for 1 s must be able to reset the power supply.  
7.1 Current Limit  
STATUS  
Required  
The power supply shall have current limit to prevent the +3.3 V, +5 V, and +12 V outputs from exceeding the  
values shown in Table 25. If the current limits are exceeded, the power supply shall shutdown and latch off. The  
latch will be cleared by toggling the PSON# signal or by an AC power interruption. The power supply shall not be  
damaged from repeated power cycling in this condition. -12 V and 5 VSB shall be protected under over current or  
shorted conditions so that no damage can occur to the power supply.  
Table 25: Over Current Protection  
Voltage  
Over Current Limit (Iout limit)  
+3.3 V  
110% minimum; 150% maximum  
+5 V  
110% minimum; 150% maximum  
110% minimum; 150% maximum  
+12V  
7.2 240VA Protection  
STATUS  
Recommended  
System designs may require user access to energized areas of the system. In these cases the power supply may  
be required to meet regulatory 240VA limits for any power rail. Since the +12V rail combined power exceeds  
240VA it must be divided into separate channels to meet this requirement. Each separate rail needs to be limited  
to less than 20A for each +12V rail. The separate +12V rails do not necessarily need to be independently  
regulated outputs. They can share a common power conversion stage. For common plane systems, the +12V rail  
is divided into either two or three rails. For split plane systems, the +12V rail is split into four rails. Refer to section  
6.4 for how the 12V rail is split between different output connectors.  
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EPS2U Power Supply Design Guide, V2.1  
Table 26: Over Current Protection  
Common Plane  
Split Plane  
Voltage  
Over Current Limit (Iout limit)  
Over Current Limit (Iout limit)  
+3.3 V  
110% minimum; 150% maximum  
110% minimum; 150% maximum  
+5 V  
110% minimum; 150% maximum  
110% minimum; 150% maximum  
15A minimum; 20A maximum  
+12V1  
+12V2  
+12V3  
+12V4  
18A minimum; 20A maximum; 22A peak1  
Peak current minimum; 20A maximum  
Peak current minimum; 20A maximum  
Peak current minimum; 20A maximum (550W only) Peak current minimum; 20A maximum  
N/A Peak current minimum; 20A maximum  
1. +12V1 peak currents shall be maintained for a minimum of 500msec. The maximum duration of the peak current exceeding  
the 240VA limit should be limited to meet safety regulations. A maximum duration of 1 second is recommended.  
7.3 Over Voltage Protection  
STATUS  
Required  
The power supply over voltage protection shall be locally sensed. The power supply shall shutdown and latch off  
after an over voltage condition occurs. This latch shall be cleared by toggling the PSON# signal or by an AC  
power interruption. Table 27 contains the over voltage limits. The values are measured at the output of the  
power supply’s connectors. The voltage shall never exceed the maximum levels when measured at the power  
pins of the power supply connector during any single point of fail. The voltage shall never trip any lower than the  
minimum levels when measured at the power pins of the power supply connector.  
Table 27: Over Voltage Limits  
Output Voltage  
MIN (V)  
MAX (V)  
+3.3 V  
3.9  
4.5  
+5 V  
5.7  
6.5  
+12V1,2,3  
-12 V  
13.3  
-13.3  
5.7  
14.5  
-14.5  
6.5  
+5 VSB  
7.4 Over Temperature Protection  
STATUS  
Recommended  
The power supply will be protected against over temperature conditions caused by loss of fan cooling or  
excessive ambient temperature. In an OTP condition the PSU will shutdown. When the power supply  
temperature drops to within specified limits, the power supply shall restore power automatically. The OTP circuit  
must have built in hysteresis such that the power supply will not oscillate on and off due to temperature recovering  
condition. The OTP trip level shall have a minimum of 4 °C of ambient temperature hysteresis.  
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EPS2U Power Supply Design Guide, V2.1  
8 Control and Indicator Functions  
The following sections define the input and output signals from the power supply.  
Signals that can be defined as low true use the following convention:  
signal# = low true  
8.1 PSON#  
STATUS  
Required  
The PSON# signal is required to remotely turn on/off the power supply. PSON# is an active low signal that turns  
on the +3.3 V, +5 V, +12 V, and -12 V power rails. When this signal is not pulled low by the system, or left open,  
the outputs (except the +5 VSB and Vbias) turn off. This signal is pulled to a standby voltage by a pull-up resistor  
internal to the power supply. Refer to Figure 3 for timing diagram.  
Table 28: PSON# Signal Characteristic  
Accepts an open collector/drain input from the system.  
Pull-up to VSB located in power supply.  
Signal Type  
PSON# = Low  
ON  
PSON# = Open or High  
OFF  
MIN  
MAX  
0 V  
1.0 V  
Logic level low (power supply ON)  
Logic level high (power supply OFF)  
Source current, Vpson = low  
2.0 V  
5 ms  
5.25 V  
4 mA  
400 ms  
50 ms  
Power up delay:  
PWOK delay:  
Tpson_on_delay  
T pson_pwok  
Hysteresis 0.3V and/or other de-bounce method  
Disabled  
1.0 V  
PS is  
2.0 V  
PS is  
enabled  
disabled  
Enabled  
0V  
1.0V  
2.0V  
5.25V  
Figure 4: PSON# Signal Characteristics  
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EPS2U Power Supply Design Guide, V2.1  
8.2 PWOK (Power OK)  
STATUS  
Required  
PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the outputs are within  
the regulation limits of the power supply. When any output voltage falls below regulation limits or when AC power  
has been removed for a time sufficiently long so that power supply operation is no longer guaranteed, PWOK will  
be deasserted to a LOW state. See Figure 3 for a representation of the timing characteristics of PWOK. The  
start of the PWOK delay time shall be inhibited as long as any power supply output is in current limit.  
Table 29: PWOK Signal Characteristics  
+5V TTL Compatible output signal  
Signal Type  
Power OK  
PWOK = High  
Power Not OK  
PWOK = Low  
MIN  
MAX  
0 V  
0.4 V  
Logic level low voltage, Isink = 4 mA  
Logic level high voltage, Isource=200 µA  
PWOK delay: Tpwok_on  
2.4 V  
200 ms  
5.25 V  
1000 ms  
100 µs  
200 ms  
PWOK rise and fall time  
1 ms  
Power down delay: T pwok_off  
8.3 Field Replacement Unit (FRU) Signals  
STATUS  
Optional  
Two pins will be allocated for the FRU information on the power supply connector. One pin is the Serial Clock  
(SCL). The second pin is used for Serial Data (SDA). Both pins are bi-directional and are used to form a serial  
bus. The FRU circuits inside the power supply must be powered off of 5 VSB output and grounded to ReturnS  
(remote sense return). The Write Control (or Write protect) pin should be tied to ReturnS inside the power supply  
so that information can be written to the EEPROM.  
8.3.1 FRU Data  
FRU data shall be stored starting in address location 8000h through 80FFh. The FRU data format shall be  
compliant with the IPMI specifications. The current versions of these specifications are available at:  
http:\\developer.intel.com/design/servers/ipmi/spec.htm.  
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EPS2U Power Supply Design Guide, V2.1  
8.3.2 FRU Data Format  
The information to be contained in the FRU device is shown in the following table.  
Table 30: FRU Device Information  
Area Type  
Description  
Common Header  
As defined by the FRU document  
Internal Use Area  
Chassis Info Area  
Board Info Area  
Not required, do not reserve  
Not applicable, do not reserve  
Not applicable, do not reserve  
8.3.2.1 Product Info Area  
Implement as defined by the IPMI FRU document. Product information shall be defined as follows:  
Table 31: FRU Device Product Information Area  
Field Name  
Field Description  
Manufacturer Name  
{Formal name of manufacturer}  
Product Name  
{Manufacturer’s model number}  
Customer part number  
Product part/model number  
Product Version  
Product Serial Number  
Asset Tag  
Customer current revision  
{Defined at time of manufacture}  
{Not used, code is zero length byte}  
{Not required}  
FRU File ID  
PAD Bytes  
{Added as necessary to allow for 8-byte offset to next area}  
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EPS2U Power Supply Design Guide, V2.1  
8.3.2.2 MultiRecord Area  
Implement as defined by the IPMI FRU document. The following record types shall be used on this power supply:  
Power Supply Information (Record Type 0x00)  
DC Output (Record Type 0x01)  
No other record types are required for the power supply.  
MultiRecord information shall be defined as follows:  
Table 32: FRU Device Product Information Area  
Field Name (PS Info)  
Field Information Definition  
Overall Capacity (watts)  
480  
Peak VA  
550  
50  
5
Inrush current (A)  
Inrush interval (ms)  
Low end input voltage range 1  
90  
High end input voltage range 1 140  
Low end input voltage range 2 180  
High end input voltage range 2 264  
A/C dropout tol. (ms)  
Binary flags  
20  
Set for: Hot Swap support, Autoswitch, and PFC  
Set for: 10 s, 550 W  
Peak Wattage  
Combined wattage  
Predictive fail tach support  
Field Name (Output)  
Set for 5 V & 3.3V combined wattage of 115 W  
Not supported, 00h value  
Field Description:  
Five outputs are to be defined from #1 to #5, as follows: +3.3 V, +5  
V, +12 V, -12V, and +5 VSB.  
Output Information  
Set for: Standby on +5 VSB, No Standby on all others.  
All other output fields  
Format per IPMI specification, using parameters in the EPS12V  
specification.  
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EPS2U Power Supply Design Guide, V2.1  
9 MTBF  
STATUS  
Recommended  
The power supply shall have a minimum MTBF at continuous operation of 1) 50,000 hours at 100% load and  
45 °C, as calculated by Bellcore RPP, or 2) 100,000 hours demonstrated at 100% load and 50 °C.  
10 Agency Requirements  
STATUS  
Recommended  
The power supply must comply with all regulatory requirements for its intended geographical market. Depending  
on the chosen market, regulatory requirements may vary. Although a power supply can be designed for  
worldwide compliance, there may be cost factors that drive different versions of supplies for different  
geographically targeted markets.  
This specification requires that the power supply meet all regulatory requirements for the intended market at the  
time of manufacturing. Typically this includes:  
UL  
CSA  
A Nordic CENELEC  
TUV  
VDE  
CISPR Class B  
FCC Class B  
The power supply, when installed in the system, shall meet immunity requirements specified in EN55024.  
Specific tests are to be EN61000-4-2, -3, -4, -5, -6, -8, -11, EN61000-3-2, -3, and JEIDI MITI standard. The  
power supply must maintain normal performance within specified limits. This testing must be completed by the  
system EMI engineer. Conformance must be designated with the European Union CE Marking. Specific  
immunity level requirements are left to customer requirements.  
- 30 -  
 
 

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